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https://github.com/capstone-engine/llvm-capstone.git
synced 2025-01-16 21:21:06 +00:00
[X86] Fix i16->f128 sitofp to promote the i16 to i32 before trying to form a libcall.
Previously one of the test cases added here gave an error.
This commit is contained in:
Craig Topper
parent
5f3bf5967b
commit
27da569a7a
@ -18430,9 +18430,6 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
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MVT VT = Op.getSimpleValueType();
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SDLoc dl(Op);
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if (VT == MVT::f128)
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return LowerF128Call(Op, DAG, RTLIB::getSINTTOFP(SrcVT, VT));
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if (SDValue Extract = vectorizeExtractedCast(Op, DAG, Subtarget))
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return Extract;
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@ -18448,25 +18445,29 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
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assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
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"Unknown SINT_TO_FP to lower!");
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bool UseSSEReg = isScalarFPTypeInSSEReg(VT);
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// These are really Legal; return the operand so the caller accepts it as
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// Legal.
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if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(VT))
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if (SrcVT == MVT::i32 && UseSSEReg)
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return Op;
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if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(VT) && Subtarget.is64Bit())
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if (SrcVT == MVT::i64 && UseSSEReg && Subtarget.is64Bit())
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return Op;
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if (SDValue V = LowerI64IntToFP_AVX512DQ(Op, DAG, Subtarget))
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return V;
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// SSE doesn't have an i16 conversion so we need to promote.
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if (SrcVT == MVT::i16 && isScalarFPTypeInSSEReg(VT)) {
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if (SrcVT == MVT::i16 && (UseSSEReg || VT == MVT::f128)) {
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SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, Src);
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return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Ext);
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}
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if (VT == MVT::f128)
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return LowerF128Call(Op, DAG, RTLIB::getSINTTOFP(SrcVT, VT));
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SDValue ValueToStore = Op.getOperand(0);
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if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(VT) &&
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!Subtarget.is64Bit())
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if (SrcVT == MVT::i64 && UseSSEReg && !Subtarget.is64Bit())
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// Bitcasting to f64 here allows us to do a single 64-bit store from
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// an SSE register, avoiding the store forwarding penalty that would come
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// with two 32-bit stores.
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@ -617,6 +617,102 @@ entry:
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ret void
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}
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define void @TestSIToFPI16_F128() nounwind {
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; X64-SSE-LABEL: TestSIToFPI16_F128:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: pushq %rax
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; X64-SSE-NEXT: movswl {{.*}}(%rip), %edi
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; X64-SSE-NEXT: callq __floatsitf
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; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
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; X64-SSE-NEXT: popq %rax
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; X64-SSE-NEXT: retq
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;
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; X32-LABEL: TestSIToFPI16_F128:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %esi
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; X32-NEXT: subl $24, %esp
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; X32-NEXT: movswl vi16, %eax
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; X32-NEXT: subl $8, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: pushl %eax
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; X32-NEXT: pushl %ecx
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; X32-NEXT: calll __floatsitf
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; X32-NEXT: addl $12, %esp
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, vf128+12
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; X32-NEXT: movl %edx, vf128+8
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; X32-NEXT: movl %ecx, vf128+4
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; X32-NEXT: movl %eax, vf128
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; X32-NEXT: addl $24, %esp
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; X32-NEXT: popl %esi
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; X32-NEXT: retl
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;
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; X64-AVX-LABEL: TestSIToFPI16_F128:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: pushq %rax
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; X64-AVX-NEXT: movswl {{.*}}(%rip), %edi
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; X64-AVX-NEXT: callq __floatsitf
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; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; X64-AVX-NEXT: popq %rax
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; X64-AVX-NEXT: retq
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entry:
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%0 = load i16, i16* @vi16, align 4
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%conv = sitofp i16 %0 to fp128
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store fp128 %conv, fp128* @vf128, align 16
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ret void
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}
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define void @TestSIToFPU16_F128() nounwind {
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; X64-SSE-LABEL: TestSIToFPU16_F128:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: pushq %rax
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; X64-SSE-NEXT: movzwl {{.*}}(%rip), %edi
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; X64-SSE-NEXT: callq __floatsitf
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; X64-SSE-NEXT: movaps %xmm0, {{.*}}(%rip)
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; X64-SSE-NEXT: popq %rax
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; X64-SSE-NEXT: retq
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;
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; X32-LABEL: TestSIToFPU16_F128:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %esi
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; X32-NEXT: subl $24, %esp
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; X32-NEXT: movzwl vi16, %eax
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; X32-NEXT: subl $8, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: pushl %eax
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; X32-NEXT: pushl %ecx
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; X32-NEXT: calll __floatunsitf
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; X32-NEXT: addl $12, %esp
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, vf128+12
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; X32-NEXT: movl %edx, vf128+8
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; X32-NEXT: movl %ecx, vf128+4
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; X32-NEXT: movl %eax, vf128
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; X32-NEXT: addl $24, %esp
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; X32-NEXT: popl %esi
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; X32-NEXT: retl
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;
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; X64-AVX-LABEL: TestSIToFPU16_F128:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: pushq %rax
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; X64-AVX-NEXT: movzwl {{.*}}(%rip), %edi
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; X64-AVX-NEXT: callq __floatsitf
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; X64-AVX-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; X64-AVX-NEXT: popq %rax
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; X64-AVX-NEXT: retq
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entry:
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%0 = load i16, i16* @vi16, align 4
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%conv = uitofp i16 %0 to fp128
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store fp128 %conv, fp128* @vf128, align 16
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ret void
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}
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define void @TestSIToFPI32_F128() nounwind {
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; X64-SSE-LABEL: TestSIToFPI32_F128:
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; X64-SSE: # %bb.0: # %entry
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@ -1159,7 +1255,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X64-SSE-LABEL: TestTruncCopysign:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: cmpl $50001, %edi # imm = 0xC351
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; X64-SSE-NEXT: jl .LBB24_2
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; X64-SSE-NEXT: jl .LBB26_2
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; X64-SSE-NEXT: # %bb.1: # %if.then
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; X64-SSE-NEXT: pushq %rax
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; X64-SSE-NEXT: callq __trunctfdf2
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@ -1168,7 +1264,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X64-SSE-NEXT: orps %xmm1, %xmm0
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; X64-SSE-NEXT: callq __extenddftf2
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; X64-SSE-NEXT: addq $8, %rsp
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; X64-SSE-NEXT: .LBB24_2: # %cleanup
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; X64-SSE-NEXT: .LBB26_2: # %cleanup
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; X64-SSE-NEXT: retq
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;
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; X32-LABEL: TestTruncCopysign:
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@ -1182,7 +1278,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: cmpl $50001, {{[0-9]+}}(%esp) # imm = 0xC351
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; X32-NEXT: jl .LBB24_4
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; X32-NEXT: jl .LBB26_4
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; X32-NEXT: # %bb.1: # %if.then
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; X32-NEXT: pushl %eax
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; X32-NEXT: pushl %ecx
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@ -1194,11 +1290,11 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X32-NEXT: testb $-128, {{[0-9]+}}(%esp)
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; X32-NEXT: flds {{\.LCPI.*}}
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; X32-NEXT: flds {{\.LCPI.*}}
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; X32-NEXT: jne .LBB24_3
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; X32-NEXT: jne .LBB26_3
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; X32-NEXT: # %bb.2: # %if.then
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; X32-NEXT: fstp %st(1)
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; X32-NEXT: fldz
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; X32-NEXT: .LBB24_3: # %if.then
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; X32-NEXT: .LBB26_3: # %if.then
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; X32-NEXT: fstp %st(0)
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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@ -1210,7 +1306,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: .LBB24_4: # %cleanup
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; X32-NEXT: .LBB26_4: # %cleanup
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; X32-NEXT: movl %edx, (%esi)
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; X32-NEXT: movl %edi, 4(%esi)
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; X32-NEXT: movl %ecx, 8(%esi)
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@ -1224,7 +1320,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X64-AVX-LABEL: TestTruncCopysign:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: cmpl $50001, %edi # imm = 0xC351
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; X64-AVX-NEXT: jl .LBB24_2
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; X64-AVX-NEXT: jl .LBB26_2
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; X64-AVX-NEXT: # %bb.1: # %if.then
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; X64-AVX-NEXT: pushq %rax
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; X64-AVX-NEXT: callq __trunctfdf2
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@ -1234,7 +1330,7 @@ define fp128 @TestTruncCopysign(fp128 %x, i32 %n) nounwind {
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; X64-AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
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; X64-AVX-NEXT: callq __extenddftf2
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; X64-AVX-NEXT: addq $8, %rsp
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; X64-AVX-NEXT: .LBB24_2: # %cleanup
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; X64-AVX-NEXT: .LBB26_2: # %cleanup
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; X64-AVX-NEXT: retq
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entry:
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%cmp = icmp sgt i32 %n, 50000
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