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https://github.com/capstone-engine/llvm-capstone.git
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[x86] add AVX512vl target for more coverage; NFC
llvm-svn: 294462
This commit is contained in:
Sanjay Patel
parent
a9b6872908
commit
28ef27e3dc
@ -1,7 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX12F --check-prefix=AVX12 --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX12F --check-prefix=AVX12 --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX12F --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl | FileCheck %s --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512VL
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; The condition vector for BLENDV* only cares about the sign bit of each element.
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; So in these tests, if we generate BLENDV*, we should be able to remove the redundant cmp op.
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@ -23,62 +24,99 @@ define <16 x i8> @signbit_sel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask)
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; Sorry 16-bit, you're not important enough to support?
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define <8 x i16> @signbit_sel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) {
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; AVX-LABEL: signbit_sel_v8i16:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vpandn %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX12F-LABEL: signbit_sel_v8i16:
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; AVX12F: # BB#0:
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; AVX12F-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX12F-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
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; AVX12F-NEXT: vpandn %xmm1, %xmm2, %xmm1
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; AVX12F-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX12F-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX12F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v8i16:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX512VL-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
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; AVX512VL-NEXT: vpandnq %xmm1, %xmm2, %xmm1
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; AVX512VL-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX512VL-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX512VL-NEXT: retq
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%tr = icmp slt <8 x i16> %mask, zeroinitializer
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%z = select <8 x i1> %tr, <8 x i16> %x, <8 x i16> %y
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ret <8 x i16> %z
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}
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define <4 x i32> @signbit_sel_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; AVX-LABEL: signbit_sel_v4i32:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX12F-LABEL: signbit_sel_v4i32:
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; AVX12F: # BB#0:
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; AVX12F-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX12F-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
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; AVX12F-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; AVX12F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v4i32:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX512VL-NEXT: vpcmpgtd %xmm2, %xmm3, %k1
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; AVX512VL-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <4 x i32> %mask, zeroinitializer
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%z = select <4 x i1> %tr, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %z
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}
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define <2 x i64> @signbit_sel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) {
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; AVX-LABEL: signbit_sel_v2i64:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX12F-LABEL: signbit_sel_v2i64:
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; AVX12F: # BB#0:
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; AVX12F-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX12F-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX12F-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
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; AVX12F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v2i64:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX512VL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
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; AVX512VL-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <2 x i64> %mask, zeroinitializer
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%z = select <2 x i1> %tr, <2 x i64> %x, <2 x i64> %y
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ret <2 x i64> %z
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}
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define <4 x float> @signbit_sel_v4f32(<4 x float> %x, <4 x float> %y, <4 x i32> %mask) {
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; AVX-LABEL: signbit_sel_v4f32:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX12F-LABEL: signbit_sel_v4f32:
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; AVX12F: # BB#0:
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; AVX12F-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX12F-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
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; AVX12F-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; AVX12F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v4f32:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX512VL-NEXT: vpcmpgtd %xmm2, %xmm3, %k1
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; AVX512VL-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <4 x i32> %mask, zeroinitializer
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%z = select <4 x i1> %tr, <4 x float> %x, <4 x float> %y
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ret <4 x float> %z
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}
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define <2 x double> @signbit_sel_v2f64(<2 x double> %x, <2 x double> %y, <2 x i64> %mask) {
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; AVX-LABEL: signbit_sel_v2f64:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX12F-LABEL: signbit_sel_v2f64:
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; AVX12F: # BB#0:
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; AVX12F-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX12F-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX12F-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
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; AVX12F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v2f64:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX512VL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
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; AVX512VL-NEXT: vblendmpd %xmm0, %xmm1, %xmm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <2 x i64> %mask, zeroinitializer
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%z = select <2 x i1> %tr, <2 x double> %x, <2 x double> %y
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ret <2 x double> %z
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@ -106,12 +144,12 @@ define <32 x i8> @signbit_sel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %mask)
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; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: signbit_sel_v32i8:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vpxor %ymm3, %ymm3, %ymm3
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; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm2
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; AVX512F-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
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; AVX512F-NEXT: retq
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; AVX512-LABEL: signbit_sel_v32i8:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpxor %ymm3, %ymm3, %ymm3
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; AVX512-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm2
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; AVX512-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
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; AVX512-NEXT: retq
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%tr = icmp slt <32 x i8> %mask, zeroinitializer
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%z = select <32 x i1> %tr, <32 x i8> %x, <32 x i8> %y
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ret <32 x i8> %z
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@ -149,6 +187,15 @@ define <16 x i16> @signbit_sel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %
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; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0
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; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v16i16:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
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; AVX512VL-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
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; AVX512VL-NEXT: vpandnq %ymm1, %ymm2, %ymm1
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; AVX512VL-NEXT: vpand %ymm2, %ymm0, %ymm0
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; AVX512VL-NEXT: vpor %ymm1, %ymm0, %ymm0
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; AVX512VL-NEXT: retq
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%tr = icmp slt <16 x i16> %mask, zeroinitializer
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%z = select <16 x i1> %tr, <16 x i16> %x, <16 x i16> %y
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ret <16 x i16> %z
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@ -182,6 +229,13 @@ define <8 x i32> @signbit_sel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask)
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; AVX512F-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
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; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v8i32:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
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; AVX512VL-NEXT: vpcmpgtd %ymm2, %ymm3, %k1
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; AVX512VL-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <8 x i32> %mask, zeroinitializer
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%z = select <8 x i1> %tr, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %z
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@ -211,6 +265,13 @@ define <4 x i64> @signbit_sel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask)
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; AVX512F-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
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; AVX512F-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v4i64:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
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; AVX512VL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
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; AVX512VL-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <4 x i64> %mask, zeroinitializer
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%z = select <4 x i1> %tr, <4 x i64> %x, <4 x i64> %y
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ret <4 x i64> %z
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@ -240,6 +301,13 @@ define <4 x double> @signbit_sel_v4f64(<4 x double> %x, <4 x double> %y, <4 x i6
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; AVX512F-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
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; AVX512F-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v4f64:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
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; AVX512VL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
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; AVX512VL-NEXT: vblendmpd %ymm0, %ymm1, %ymm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <4 x i64> %mask, zeroinitializer
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%z = select <4 x i1> %tr, <4 x double> %x, <4 x double> %y
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ret <4 x double> %z
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@ -274,6 +342,13 @@ define <4 x double> @signbit_sel_v4f64_small_mask(<4 x double> %x, <4 x double>
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; AVX512F-NEXT: vpmovsxdq %xmm2, %ymm2
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; AVX512F-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: signbit_sel_v4f64_small_mask:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX512VL-NEXT: vpcmpgtd %xmm2, %xmm3, %k1
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; AVX512VL-NEXT: vblendmpd %ymm0, %ymm1, %ymm0 {%k1}
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; AVX512VL-NEXT: retq
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%tr = icmp slt <4 x i32> %mask, zeroinitializer
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%z = select <4 x i1> %tr, <4 x double> %x, <4 x double> %y
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ret <4 x double> %z
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@ -306,12 +381,12 @@ define <8 x double> @signbit_sel_v8f64(<8 x double> %x, <8 x double> %y, <8 x i6
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; AVX2-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: signbit_sel_v8f64:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vpxord %zmm3, %zmm3, %zmm3
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; AVX512F-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
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; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}
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; AVX512F-NEXT: retq
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; AVX512-LABEL: signbit_sel_v8f64:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpxord %zmm3, %zmm3, %zmm3
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; AVX512-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
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; AVX512-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}
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; AVX512-NEXT: retq
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%tr = icmp slt <8 x i64> %mask, zeroinitializer
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%z = select <8 x i1> %tr, <8 x double> %x, <8 x double> %y
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ret <8 x double> %z
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