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[X86] Rename matchShuffleAsRotate - matchShuffleAsByteRotate. NFCI.

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A matchShuffleAsBitRotate variant will be added soon and we need to make the difference more obvious.
This commit is contained in:
Simon Pilgrim 2020-02-09 14:23:19 +00:00
parent 9d223a0106
commit 29621b2534
1 changed files with 5 additions and 4 deletions
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9
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -11665,10 +11665,11 @@ static SDValue lowerShuffleAsDecomposedShuffleBlend(
return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
}
/// Try to lower a vector shuffle as a rotation.
/// Try to lower a vector shuffle as a byte rotation.
///
/// This is used for support PALIGNR for SSSE3 or VALIGND/Q for AVX512.
static int matchShuffleAsRotate(SDValue &V1, SDValue &V2, ArrayRef<int> Mask) {
static int matchShuffleAsByteRotate(SDValue &V1, SDValue &V2,
ArrayRef<int> Mask) {
int NumElts = Mask.size();
// We need to detect various ways of spelling a rotation:
@ -11763,7 +11764,7 @@ static int matchShuffleAsByteRotate(MVT VT, SDValue &V1, SDValue &V2,
if (!is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask))
return -1;
int Rotation = matchShuffleAsRotate(V1, V2, RepeatedMask);
int Rotation = matchShuffleAsByteRotate(V1, V2, RepeatedMask);
if (Rotation <= 0)
return -1;
@ -11843,7 +11844,7 @@ static SDValue lowerShuffleAsVALIGN(const SDLoc &DL, MVT VT, SDValue V1,
&& "VLX required for 128/256-bit vectors");
SDValue Lo = V1, Hi = V2;
int Rotation = matchShuffleAsRotate(Lo, Hi, Mask);
int Rotation = matchShuffleAsByteRotate(Lo, Hi, Mask);
if (Rotation <= 0)
return SDValue();