Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-11-27 23:51:56 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

[RISCV] Remove overly restrictive assert from negateFMAOpcode.

Browse Source 
It's possible that both multiplicands are being negated. This won't
change the opcode, but we can delete the two negates. Allow this
case to get through negateFMAOpcode.

I think D152260 will also fix this test case, but in the future
it may be possible for an fneg to appear after we've already converted
to RISCVISD opcodes in which case D152260 won't help.

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D152296
This commit is contained in:
Craig Topper 2023-06-06 18:34:15 -07:00
parent d4c5b45293
commit 2b09f53b32
2 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -11412,8 +11412,6 @@ static SDValue performBITREVERSECombine(SDNode *N, SelectionDAG &DAG,
// multiply result and/or the accumulator.
// NOTE: Only supports RVV operations with VL.
static unsigned negateFMAOpcode(unsigned Opcode, bool NegMul, bool NegAcc) {
assert((NegMul || NegAcc) && "Not negating anything?");
// Negating the multiply result changes ADD<->SUB and toggles 'N'.
if (NegMul) {
// clang-format off

13
llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
View File

@ -7708,3 +7708,16 @@ define <vscale x 8 x double> @vfnmsub_vf_nxv8f64_neg_splat_unmasked_commute(<vsc
%v = call <vscale x 8 x double> @llvm.vp.fma.nxv8f64(<vscale x 8 x double> %negvb, <vscale x 8 x double> %va, <vscale x 8 x double> %vc, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x double> %v
}
define <vscale x 1 x half> @vfma_vv_nxv1f16_double_neg(<vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfma_vv_nxv1f16_double_neg:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfmadd.vv v9, v8, v10, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%nega = call <vscale x 1 x half> @llvm.vp.fneg.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x i1> %m, i32 %evl)
%negb = call <vscale x 1 x half> @llvm.vp.fneg.nxv1f16(<vscale x 1 x half> %b, <vscale x 1 x i1> %m, i32 %evl)
%v = call <vscale x 1 x half> @llvm.vp.fma.nxv1f16(<vscale x 1 x half> %nega, <vscale x 1 x half> %negb, <vscale x 1 x half> %c, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
}