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[SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

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Adds the SVE vector and predicate registers to the list of known registers.

Patch by Kerry McLaughlin.

Reviewers: erichkeane, sdesmalen, rengolin

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D64739

llvm-svn: 366878
This commit is contained in:
Sander de Smalen 2019-07-24 08:42:34 +00:00
parent ec4d8cdd59
commit 2b290885d9
2 changed files with 24 additions and 2 deletions
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13
clang/lib/Basic/Targets/AArch64.cpp
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@ -351,10 +351,19 @@ const char *const AArch64TargetInfo::GCCRegNames[] = {
"d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
"d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
// Vector registers
// Neon vector registers
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
"v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
"v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
"v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// SVE vector registers
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10",
"z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
"z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
// SVE predicate registers
"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10",
"p11", "p12", "p13", "p14", "p15"
};
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {

13
clang/test/CodeGen/aarch64-sve-inline-asm.c Normal file
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@ -0,0 +1,13 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK
void test_sve_asm() {
asm volatile(
"ptrue p0.d\n"
"ptrue p15.d\n"
"add z0.d, p0/m, z0.d, z0.d\n"
"add z31.d, p0/m, z31.d, z31.d\n"
:
:
: "z0", "z31", "p0", "p15");
// CHECK: "~{z0},~{z31},~{p0},~{p15}"
}