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[ARM][AArch64] Make ACLE __clzl/__clzll return unsigned int instead of unsigned long/uint64_t.
Use unsigned long in place of uint32_t for both clz and cls. As far as I can tell this matches what ACLE defines and what gcc implements. Noticed while investigating fixing https://github.com/llvm/llvm-project/issues/63113 Reviewed By: tmatheson Differential Revision: https://reviews.llvm.org/D154910
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@ -138,28 +138,28 @@ __rorl(unsigned long __x, uint32_t __y) {
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/* CLZ */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clz(uint32_t __t) {
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return (uint32_t)__builtin_clz(__t);
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return (unsigned int)__builtin_clz(__t);
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}
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static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clzl(unsigned long __t) {
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return (unsigned long)__builtin_clzl(__t);
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return (unsigned int)__builtin_clzl(__t);
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}
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static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clzll(uint64_t __t) {
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return (uint64_t)__builtin_clzll(__t);
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return (unsigned int)__builtin_clzll(__t);
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}
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/* CLS */
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__cls(uint32_t __t) {
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return __builtin_arm_cls(__t);
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}
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clsl(unsigned long __t) {
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#if __SIZEOF_LONG__ == 4
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return __builtin_arm_cls(__t);
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@ -168,7 +168,7 @@ __clsl(unsigned long __t) {
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#endif
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}
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static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
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static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
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__clsll(uint64_t __t) {
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return __builtin_arm_cls64(__t);
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}
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@ -332,7 +332,7 @@ uint64_t test_rorll(uint64_t x, uint32_t y) {
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// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false)
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// ARM-NEXT: ret i32 [[TMP0]]
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//
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uint32_t test_clz(uint32_t t) {
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unsigned test_clz(uint32_t t) {
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return __clz(t);
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}
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@ -345,10 +345,9 @@ uint32_t test_clz(uint32_t t) {
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// AArch64-NEXT: entry:
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// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)
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// AArch64-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
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// AArch64-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64
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// AArch64-NEXT: ret i64 [[CONV_I]]
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// AArch64-NEXT: ret i32 [[CAST_I]]
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//
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long test_clzl(long t) {
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unsigned test_clzl(unsigned long t) {
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return __clzl(t);
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}
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@ -356,10 +355,9 @@ long test_clzl(long t) {
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// ARM-NEXT: entry:
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// ARM-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)
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// ARM-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
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// ARM-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64
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// ARM-NEXT: ret i64 [[CONV_I]]
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// ARM-NEXT: ret i32 [[CAST_I]]
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//
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uint64_t test_clzll(uint64_t t) {
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unsigned test_clzll(uint64_t t) {
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return __clzll(t);
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}
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