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[AMDGPU] Regenerate always-uniform.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.readfirstlane(i32)
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; GCN-LABEL: readfirstlane_uniform
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; GCN: s_load_dwordx4 s[[[IN_ADDR:[0-9]+]]:3], s[4:5], 0x0
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; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0
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; GCN: s_add_u32 s[[LOAD_ADDR:[0-9]+]], s[[IN_ADDR]], s[[SCALAR]]
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; GCN: s_load_dword s{{[0-9]+}}, s[[[LOAD_ADDR]]
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define amdgpu_kernel void @readfirstlane_uniform(ptr addrspace(1) noalias nocapture readonly, ptr addrspace(1) noalias nocapture readonly) {
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; GCN-LABEL: readfirstlane_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: v_readfirstlane_b32 s4, v0
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; GCN-NEXT: s_mov_b32 s5, 0
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; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_add_u32 s0, s0, s4
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; GCN-NEXT: s_addc_u32 s1, s1, s5
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; GCN-NEXT: s_load_dword s4, s[0:1], 0x0
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; GCN-NEXT: s_add_u32 s0, s2, 40
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; GCN-NEXT: s_addc_u32 s1, s3, 0
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v2, s4
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_endpgm
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid)
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%idx = zext i32 %scalar to i64
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