Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-12-16 20:41:44 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[RISCV] Add a special caes to performVFMADD_VLCombine to support the multiplicand being the same value.

Browse Source 
The one use check will fail if there are two uses in the same
instruction. Add a special case for this.
This commit is contained in:
Craig Topper 2023-05-24 17:25:33 -07:00
parent 5be5746b6e
commit 2f3e17566b
2 changed files with 28 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -11265,7 +11265,8 @@ static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG) {
// TODO: Refactor to handle more complex cases similar to
// combineBinOp_VLToVWBinOp_VL.
if (!Op0.hasOneUse() || !Op1.hasOneUse())
if ((!Op0.hasOneUse() || !Op1.hasOneUse()) &&
(Op0 != Op1 || !Op0->hasNUsesOfValue(2, 0)))
return SDValue();
// Check the mask and VL are the same.

26
llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
View File

@ -754,3 +754,29 @@ define <vscale x 8 x double> @vfmacc_vv_nxv8f64_nxv8f16_unmasked(<vscale x 8 x h
%v = call <vscale x 8 x double> @llvm.vp.fma.nxv8f64(<vscale x 8 x double> %aext, <vscale x 8 x double> %bext, <vscale x 8 x double> %c, <vscale x 8 x i1> %allones, i32 %evl)
ret <vscale x 8 x double> %v
}
define <vscale x 1 x float> @vfmacc_squared_nxv1f32(<vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 1 x float> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfmacc_squared_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwmacc.vv v10, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%aext = call <vscale x 1 x float> @llvm.vp.fpext.nxv1f32.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x i1> %m, i32 %evl)
%v = call <vscale x 1 x float> @llvm.vp.fma.nxv1f32(<vscale x 1 x float> %aext, <vscale x 1 x float> %aext, <vscale x 1 x float> %c, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x float> %v
}
define <vscale x 1 x float> @vfmacc_squared_nxv1f32_unmasked(<vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 1 x float> %c, i32 zeroext %evl) {
; CHECK-LABEL: vfmacc_squared_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwmacc.vv v10, v8, v8
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%splat = insertelement <vscale x 1 x i1> poison, i1 -1, i32 0
%allones = shufflevector <vscale x 1 x i1> %splat, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%aext = call <vscale x 1 x float> @llvm.vp.fpext.nxv1f32.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x i1> %allones, i32 %evl)
%v = call <vscale x 1 x float> @llvm.vp.fma.nxv1f32(<vscale x 1 x float> %aext, <vscale x 1 x float> %aext, <vscale x 1 x float> %c, <vscale x 1 x i1> %allones, i32 %evl)
ret <vscale x 1 x float> %v
}