diff --git a/bolt/lib/Core/Relocation.cpp b/bolt/lib/Core/Relocation.cpp
index c1ff2cee9cdc..25a3fc0decb4 100644
--- a/bolt/lib/Core/Relocation.cpp
+++ b/bolt/lib/Core/Relocation.cpp
@@ -168,16 +168,17 @@ bool skipRelocationProcessX86(uint64_t Type, uint64_t Contents) {
 bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   auto IsMov = [](uint64_t Contents) -> bool {
     // The bits 28-23 are 0b100101
-    if ((Contents & 0x1f800000) == 0x12800000)
-      return true;
-    return false;
+    return (Contents & 0x1f800000) == 0x12800000;
   };
 
   auto IsB = [](uint64_t Contents) -> bool {
     // The bits 31-26 are 0b000101
-    if ((Contents & 0xfc000000) == 0x14000000)
-      return true;
-    return false;
+    return (Contents & 0xfc000000) == 0x14000000;
+  };
+
+  auto IsAdr = [](uint64_t Contents) -> bool {
+    // The bits 31-24 are 0b0xx10000
+    return (Contents & 0x9f000000) == 0x10000000;
   };
 
   auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
@@ -205,7 +206,7 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   }
   }
 
-  // The ld might replace load/store instruction with jump and
+  // The linker might replace load/store instruction with jump and
   // veneer due to errata 843419
   // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d
   // Thus load/store relocations for these instructions must be ignored
@@ -223,6 +224,18 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   }
   }
 
+  // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
+  switch (Type) {
+  default:
+    break;
+  case ELF::R_AARCH64_ADR_PREL_PG_HI21:
+  case ELF::R_AARCH64_ADD_ABS_LO12_NC:
+  case ELF::R_AARCH64_ADR_GOT_PAGE:
+  case ELF::R_AARCH64_LD64_GOT_LO12_NC:
+    if (IsAdr(Contents))
+      return true;
+  }
+
   return false;
 }
 
diff --git a/bolt/test/AArch64/Inputs/skip-got-rel.yaml b/bolt/test/AArch64/Inputs/skip-got-rel.yaml
new file mode 100644
index 000000000000..1c89d086af6b
--- /dev/null
+++ b/bolt/test/AArch64/Inputs/skip-got-rel.yaml
@@ -0,0 +1,172 @@
+--- !ELF
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diff --git a/bolt/test/AArch64/skip-got-rel.test b/bolt/test/AArch64/skip-got-rel.test
new file mode 100644
index 000000000000..4acf397d7bf4
--- /dev/null
+++ b/bolt/test/AArch64/skip-got-rel.test
@@ -0,0 +1,8 @@
+// This test checks that the binary with relaxed ADRP+LDR instructions is
+// processed normally with BOLT and the ADR instruction address is recognized
+// normally.
+
+RUN: yaml2obj %p/Inputs/skip-got-rel.yaml &> %t.exe
+RUN: llvm-bolt %t.exe -o /dev/null -print-cfg -print-only=_start | FileCheck %s
+
+CHECK: adr	x0, foo2
diff --git a/bolt/test/runtime/plt-lld.test b/bolt/test/runtime/plt-lld.test
index f2c4babd5e3d..b52652f606dd 100644
--- a/bolt/test/runtime/plt-lld.test
+++ b/bolt/test/runtime/plt-lld.test
@@ -1,9 +1,16 @@
 // This test checks that the pointers to PLT are properly updated.
 // The test is using lld linker.
 
-// RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
-// RUN:    -o %t.lld.exe -Wl,-q
-// RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
-// RUN: %t.lld.bolt.exe | FileCheck %s
+// Non-PIE:
+RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
+RUN:    -o %t.lld.exe -Wl,-q
+RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
+RUN: %t.lld.bolt.exe | FileCheck %s
 
-// CHECK: Test completed
+// PIE:
+RUN: %clang %cflags -fPIC -pie %p/../Inputs/plt.c -fuse-ld=lld \
+RUN:    -o %t.lld.pie.exe -Wl,-q
+RUN: llvm-bolt %t.lld.pie.exe -o %t.lld.bolt.pie.exe -use-old-text=0 -lite=0
+RUN: %t.lld.bolt.pie.exe | FileCheck %s
+
+CHECK: Test completed