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[AArch64][FMV] Fix name mangling.

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Put features into function version name in increasing priority order.

Differential Revision: https://reviews.llvm.org/D150800
This commit is contained in:
Pavel Iliin 2023-05-17 18:14:01 +01:00
parent f7d1baa414
commit 30b0fdfff1
5 changed files with 34 additions and 23 deletions
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13
clang/lib/CodeGen/CodeGenModule.cpp
View File

@ -1362,8 +1362,13 @@ static void AppendTargetVersionMangling(const CodeGenModule &CGM,
if (Attr->isDefaultVersion())
return;
Out << "._";
const TargetInfo &TI = CGM.getTarget();
llvm::SmallVector<StringRef, 8> Feats;
Attr->getFeatures(Feats);
llvm::stable_sort(Feats, [&TI](const StringRef FeatL, const StringRef FeatR) {
return TI.multiVersionSortPriority(FeatL) <
TI.multiVersionSortPriority(FeatR);
});
for (const auto &Feat : Feats) {
Out << 'M';
Out << Feat;
@ -1415,13 +1420,19 @@ static void AppendTargetClonesMangling(const CodeGenModule &CGM,
const TargetClonesAttr *Attr,
unsigned VersionIndex,
raw_ostream &Out) {
if (CGM.getTarget().getTriple().isAArch64()) {
const TargetInfo &TI = CGM.getTarget();
if (TI.getTriple().isAArch64()) {
StringRef FeatureStr = Attr->getFeatureStr(VersionIndex);
if (FeatureStr == "default")
return;
Out << "._";
SmallVector<StringRef, 8> Features;
FeatureStr.split(Features, "+");
llvm::stable_sort(Features,
[&TI](const StringRef FeatL, const StringRef FeatR) {
return TI.multiVersionSortPriority(FeatL) <
TI.multiVersionSortPriority(FeatR);
});
for (auto &Feat : Features) {
Out << 'M';
Out << Feat;

20
clang/test/CodeGen/attr-target-clones-aarch64.c
View File

@ -32,7 +32,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc._MaesMlse(
// CHECK-LABEL: @ftc._MlseMaes(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
// CHECK: Function Attrs: noinline nounwind optnone
@ -52,7 +52,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc._MaesMlse
// CHECK-NEXT: ret ptr @ftc._MlseMaes
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
@ -68,7 +68,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
// CHECK-LABEL: @ftc_def._Msha2Mmemtag2(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
// CHECK: Function Attrs: noinline nounwind optnone
@ -84,7 +84,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
// CHECK-NEXT: ret ptr @ftc_def._Msha2Mmemtag2
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
@ -120,7 +120,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 3
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_dup2._McrcMdotprod(
// CHECK-LABEL: @ftc_dup2._MdotprodMcrc(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 3
// CHECK: Function Attrs: noinline nounwind optnone
@ -136,7 +136,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod
// CHECK-NEXT: ret ptr @ftc_dup2._MdotprodMcrc
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256
@ -192,7 +192,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @ftc_inline1._MpredresMrcpc
// CHECK-NEXT: ret ptr @ftc_inline1._MrcpcMpredres
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 513
@ -232,7 +232,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
// CHECK-NEXT: ret ptr @ftc_inline3._MsveMsb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
@ -248,7 +248,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_inline1._MpredresMrcpc(
// CHECK-LABEL: @ftc_inline1._MrcpcMpredres(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
// CHECK: Function Attrs: noinline nounwind optnone
@ -276,7 +276,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 3
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_inline3._MsbMsve(
// CHECK-LABEL: @ftc_inline3._MsveMsb(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 3
// CHECK: Function Attrs: noinline nounwind optnone

12
clang/test/CodeGen/attr-target-version.c
View File

@ -119,7 +119,7 @@ int hoo(void) {
// CHECK-LABEL: @fmv(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
// CHECK-LABEL: @fmv_one._Mls64Msimd(
// CHECK-LABEL: @fmv_one._MsimdMls64(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
// CHECK-LABEL: @fmv_one._Mdpb(
@ -137,7 +137,7 @@ int hoo(void) {
// CHECK-LABEL: @fmv_two._Mdgh(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 3
// CHECK-LABEL: @fmv_two._Mfp16Msimd(
// CHECK-LABEL: @fmv_two._MsimdMfp16(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 4
// CHECK-LABEL: @fmv_two(
@ -229,10 +229,10 @@ int hoo(void) {
// CHECK-NEXT: ret ptr @fmv
// CHECK-LABEL: @fmv_one.resolver(
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: ret ptr @fmv_one._Mls64Msimd
// CHECK-NEXT: ret ptr @fmv_one._MsimdMls64
// CHECK-LABEL: @fmv_two.resolver(
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
// CHECK-NEXT: ret ptr @fmv_two._MsimdMfp16
// CHECK-LABEL: @fmv_e(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 20
@ -262,7 +262,7 @@ int hoo(void) {
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16MfcmaMsmeMfp16
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16Mfp16MfcmaMsme
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 893353197568
@ -407,7 +407,7 @@ int hoo(void) {
// CHECK-LABEL: @fmv_inline._Msha1MpmullMf64mm(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
// CHECK-LABEL: @fmv_inline._Mfp16MfcmaMsmeMfp16(
// CHECK-LABEL: @fmv_inline._Mfp16Mfp16MfcmaMsme(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 2
// CHECK-LABEL: @fmv_inline._Msha3Mi8mmMf32mm(

8
clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
View File

@ -108,7 +108,7 @@ void run_foo_tml() {
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs
// CHECK-NEXT: ret ptr @_ZN7MyClassIssE7foo_tmlEv._MssbsMsme-f64f64
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
@ -128,7 +128,7 @@ void run_foo_tml() {
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._MssbsMsme-f64f64
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
@ -157,7 +157,7 @@ void run_foo_tml() {
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: ret i32 1
// CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs(
// CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv._MssbsMsme-f64f64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
@ -175,7 +175,7 @@ void run_foo_tml() {
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK-NEXT: ret i32 2
// CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs(
// CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv._MssbsMsme-f64f64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8

4
clang/test/CodeGenCXX/attr-target-version.cpp
View File

@ -27,7 +27,7 @@ int bar() {
// CHECK: @_Z3fooi.ifunc = weak_odr ifunc i32 (i32), ptr @_Z3fooi.resolver
// CHECK: @_Z3foov.ifunc = weak_odr ifunc i32 (), ptr @_Z3foov.resolver
// CHECK-LABEL: @_Z3fooi._Msme-f64f64Mbf16(
// CHECK-LABEL: @_Z3fooi._Mbf16Msme-f64f64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[TMP0:%.*]], ptr [[DOTADDR]], align 4
@ -105,7 +105,7 @@ int bar() {
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_Z3fooi._Msme-f64f64Mbf16
// CHECK-NEXT: ret ptr @_Z3fooi._Mbf16Msme-f64f64
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @_Z3fooi
// CHECK-LABEL: @_Z3foov.resolver(