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AMDGPU: Select branch on undef to uniform scc branch
llvm-svn: 289877
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68e58b4b60
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@ -1458,6 +1458,12 @@ bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
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void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
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SDValue Cond = N->getOperand(1);
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if (Cond.isUndef()) {
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CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
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N->getOperand(2), N->getOperand(0));
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return;
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}
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if (isCBranchSCC(N)) {
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// This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
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SelectCode(N);
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@ -1762,6 +1762,15 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
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MI.eraseFromParent();
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return BB;
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}
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case AMDGPU::SI_BR_UNDEF: {
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const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
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const DebugLoc &DL = MI.getDebugLoc();
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MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
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.addOperand(MI.getOperand(0));
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Br->getOperand(1).setIsUndef(true); // read undef SCC
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MI.eraseFromParent();
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return BB;
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}
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default:
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return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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}
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@ -246,6 +246,12 @@ def SI_KILL_TERMINATOR : SPseudoInstSI <
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} // End Uses = [EXEC], Defs = [EXEC,VCC]
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// Branch on undef scc. Used to avoid intermediate copy from
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// IMPLICIT_DEF to SCC.
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def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins sopp_brtarget:$simm16)> {
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let isTerminator = 1;
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let usesCustomInserter = 1;
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}
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def SI_PS_LIVE : PseudoInstSI <
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(outs SReg_64:$dst), (ins),
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@ -27,7 +27,7 @@
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; GCN-LABEL: {{^}}sink_ubfe_i32:
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; GCN-NOT: lshr
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; GCN: s_cbranch_vccnz
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; GCN: s_cbranch_scc1
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008
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; GCN: BB0_2:
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@ -121,7 +121,7 @@ ret:
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; GCN-LABEL: {{^}}sink_ubfe_i16:
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; GCN-NOT: lshr
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; VI: s_bfe_u32 s0, s0, 0xc0004
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; GCN: s_cbranch_vccnz
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; GCN: s_cbranch_scc1
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; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004
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; VI: s_and_b32 s0, s0, 0xff
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@ -175,12 +175,13 @@ ret:
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint:
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30
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; GCN: s_cbranch_vccnz BB3_2
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; GCN: s_cbranch_scc1 BB3_2
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30
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; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0xff
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; GCN: BB3_2:
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; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30
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; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0x7f
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; GCN: BB3_3:
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@ -225,7 +226,7 @@ ret:
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; GCN-LABEL: {{^}}sink_ubfe_i64_low32:
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; GCN: s_cbranch_vccnz BB4_2
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; GCN: s_cbranch_scc1 BB4_2
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f
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@ -273,7 +274,7 @@ ret:
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_high32:
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; GCN: s_cbranch_vccnz BB5_2
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; GCN: s_cbranch_scc1 BB5_2
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003
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; GCN: BB5_2:
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@ -4,7 +4,7 @@
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; SILowerI1Copies was not handling IMPLICIT_DEF
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; SI-LABEL: {{^}}br_implicit_def:
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; SI: BB#0:
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; SI-NEXT: s_cbranch_vccnz
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; SI-NEXT: s_cbranch_scc1
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define void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 {
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bb:
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br i1 undef, label %bb1, label %bb2
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@ -5,7 +5,7 @@
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; Mask should be in original state after executed unreachable block
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; GCN-LABEL: {{^}}main:
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; GCN: s_cbranch_vccnz [[RET_BB:BB[0-9]+_[0-9]+]]
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; GCN: s_cbranch_scc1 [[RET_BB:BB[0-9]+_[0-9]+]]
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; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN-NEXT: s_xor_b64 [[XOR_EXEC:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_EXEC]]
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@ -37,7 +37,7 @@ bb5: ; preds = %bb3, %bb1
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; OPT-NOT: call i1 @llvm.amdgcn.loop
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; GCN-LABEL: {{^}}annotate_ret_noloop:
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; GCN: s_cbranch_vccnz
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; GCN: s_cbranch_scc1
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; GCN: s_endpgm
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; GCN: .Lfunc_end1
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define void @annotate_ret_noloop(<4 x float> addrspace(1)* noalias nocapture readonly %arg) #0 {
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@ -263,7 +263,7 @@ exit:
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; CHECK-NEXT: s_endpgm
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; CHECK: [[KILLBB:BB[0-9]+_[0-9]+]]:
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; CHECK-NEXT: s_cbranch_vccz [[PHIBB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: s_cbranch_scc0 [[PHIBB:BB[0-9]+_[0-9]+]]
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; CHECK: [[PHIBB]]:
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; CHECK: v_cmp_eq_f32_e32 vcc, 0, [[PHIREG]]
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@ -40,7 +40,7 @@ for.end: ; preds = %for.body, %entry
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; COMMON-LABEL: {{^}}branch_false:
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; SI: s_cbranch_vccnz
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; SI: s_cbranch_vccnz
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; SI: s_cbranch_scc1
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; SI: s_endpgm
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define void @branch_false(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 {
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entry:
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@ -76,8 +76,8 @@ for.end: ; preds = %for.body, %entry
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}
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; COMMON-LABEL: {{^}}branch_undef:
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; SI: s_cbranch_vccnz
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; SI: s_cbranch_vccnz
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; SI: s_cbranch_scc1
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; SI: s_cbranch_scc1
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; SI: s_endpgm
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define void @branch_undef(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 {
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entry:
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