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https://github.com/capstone-engine/llvm-capstone.git
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[llvm-exegesis][NFC] internal changes
Summary: BitVectors are now cached to lower memory utilization. Instructions have reference semantics. Reviewers: courbet Subscribers: sdardis, tschuett, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71653
This commit is contained in:
Guillaume Chatelet
parent
d3d1ca14ce
commit
32d384c020
@ -15,8 +15,8 @@ CodeTemplate::CodeTemplate(CodeTemplate &&) = default;
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CodeTemplate &CodeTemplate::operator=(CodeTemplate &&) = default;
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InstructionTemplate::InstructionTemplate(const Instruction &Instr)
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: Instr(Instr), VariableValues(Instr.Variables.size()) {}
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InstructionTemplate::InstructionTemplate(const Instruction *Instr)
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: Instr(Instr), VariableValues(Instr->Variables.size()) {}
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InstructionTemplate::InstructionTemplate(InstructionTemplate &&) = default;
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@ -29,7 +29,7 @@ InstructionTemplate &InstructionTemplate::
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operator=(const InstructionTemplate &) = default;
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unsigned InstructionTemplate::getOpcode() const {
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return Instr.Description->getOpcode();
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return Instr->Description.getOpcode();
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}
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MCOperand &InstructionTemplate::getValueFor(const Variable &Var) {
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@ -41,23 +41,23 @@ const MCOperand &InstructionTemplate::getValueFor(const Variable &Var) const {
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}
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MCOperand &InstructionTemplate::getValueFor(const Operand &Op) {
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return getValueFor(Instr.Variables[Op.getVariableIndex()]);
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return getValueFor(Instr->Variables[Op.getVariableIndex()]);
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}
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const MCOperand &InstructionTemplate::getValueFor(const Operand &Op) const {
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return getValueFor(Instr.Variables[Op.getVariableIndex()]);
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return getValueFor(Instr->Variables[Op.getVariableIndex()]);
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}
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bool InstructionTemplate::hasImmediateVariables() const {
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return any_of(Instr.Variables, [this](const Variable &Var) {
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return Instr.getPrimaryOperand(Var).isImmediate();
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return any_of(Instr->Variables, [this](const Variable &Var) {
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return Instr->getPrimaryOperand(Var).isImmediate();
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});
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}
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MCInst InstructionTemplate::build() const {
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MCInst Result;
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Result.setOpcode(Instr.Description->Opcode);
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for (const auto &Op : Instr.Operands)
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Result.setOpcode(Instr->Description.Opcode);
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for (const auto &Op : Instr->Operands)
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if (Op.isExplicit())
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Result.addOperand(getValueFor(Op));
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return Result;
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@ -23,7 +23,7 @@ namespace exegesis {
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// A template for an Instruction holding values for each of its Variables.
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struct InstructionTemplate {
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InstructionTemplate(const Instruction &Instr);
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InstructionTemplate(const Instruction *Instr);
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InstructionTemplate(const InstructionTemplate &); // default
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InstructionTemplate &operator=(const InstructionTemplate &); // default
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@ -36,13 +36,16 @@ struct InstructionTemplate {
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MCOperand &getValueFor(const Operand &Op);
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const MCOperand &getValueFor(const Operand &Op) const;
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bool hasImmediateVariables() const;
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const Instruction &getInstr() const { return *Instr; }
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ArrayRef<MCOperand> getVariableValues() const { return VariableValues; }
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// Builds an MCInst from this InstructionTemplate setting its operands
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// to the corresponding variable values. Precondition: All VariableValues must
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// be set.
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MCInst build() const;
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Instruction Instr;
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private:
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const Instruction *Instr;
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SmallVector<MCOperand, 4> VariableValues;
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};
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@ -37,8 +37,8 @@ struct ExecutionClass {
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static constexpr size_t kMaxAliasingInstructions = 10;
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static std::vector<Instruction>
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computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
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static std::vector<const Instruction *>
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computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
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size_t MaxAliasingInstructions,
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const BitVector &ForbiddenRegisters) {
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// Randomly iterate the set of instructions.
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@ -47,15 +47,15 @@ computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
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std::iota(Opcodes.begin(), Opcodes.end(), 0U);
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std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
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std::vector<Instruction> AliasingInstructions;
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std::vector<const Instruction *> AliasingInstructions;
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for (const unsigned OtherOpcode : Opcodes) {
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if (OtherOpcode == Instr.Description->getOpcode())
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if (OtherOpcode == Instr->Description.getOpcode())
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continue;
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const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
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if (OtherInstr.hasMemoryOperands())
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continue;
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if (Instr.hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
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AliasingInstructions.push_back(OtherInstr);
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if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
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AliasingInstructions.push_back(&OtherInstr);
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if (AliasingInstructions.size() >= MaxAliasingInstructions)
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break;
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}
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@ -81,7 +81,7 @@ static ExecutionMode getExecutionModes(const Instruction &Instr,
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}
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static void appendCodeTemplates(const LLVMState &State,
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const Instruction &Instr,
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const Instruction *Instr,
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const BitVector &ForbiddenRegisters,
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ExecutionMode ExecutionModeBit,
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StringRef ExecutionClassDescription,
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@ -109,7 +109,7 @@ static void appendCodeTemplates(const LLVMState &State,
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case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS: {
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// Making the execution of this instruction serial by selecting one def
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// register to alias with one use register.
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const AliasingConfigurations SelfAliasing(Instr, Instr);
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const AliasingConfigurations SelfAliasing(*Instr, *Instr);
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assert(!SelfAliasing.empty() && !SelfAliasing.hasImplicitAliasing() &&
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"Instr must alias itself explicitly");
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InstructionTemplate IT(Instr);
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@ -125,10 +125,10 @@ static void appendCodeTemplates(const LLVMState &State,
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}
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case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: {
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// Select back-to-back non-memory instruction.
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for (const auto OtherInstr : computeAliasingInstructions(
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for (const auto *OtherInstr : computeAliasingInstructions(
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State, Instr, kMaxAliasingInstructions, ForbiddenRegisters)) {
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const AliasingConfigurations Forward(Instr, OtherInstr);
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const AliasingConfigurations Back(OtherInstr, Instr);
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const AliasingConfigurations Forward(*Instr, *OtherInstr);
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const AliasingConfigurations Back(*OtherInstr, *Instr);
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InstructionTemplate ThisIT(Instr);
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InstructionTemplate OtherIT(OtherInstr);
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if (!Forward.hasImplicitAliasing())
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@ -158,7 +158,7 @@ LatencySnippetGenerator::generateCodeTemplates(
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const ExecutionMode EM = getExecutionModes(Instr, ForbiddenRegisters);
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for (const auto EC : kExecutionClasses) {
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for (const auto ExecutionModeBit : getExecutionModeBits(EM & EC.Mask))
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appendCodeTemplates(State, Instr, ForbiddenRegisters, ExecutionModeBit,
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appendCodeTemplates(State, &Instr, ForbiddenRegisters, ExecutionModeBit,
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EC.Description, Results);
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if (!Results.empty())
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break;
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@ -17,10 +17,7 @@
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namespace llvm {
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namespace exegesis {
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unsigned Variable::getIndex() const {
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assert(Index >= 0 && "Index must be set");
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return Index;
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}
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unsigned Variable::getIndex() const { return *Index; }
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unsigned Variable::getPrimaryOperandIndex() const {
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assert(!TiedOperands.empty());
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@ -36,10 +33,7 @@ bool Variable::hasTiedOperands() const {
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return TiedOperands.size() > 1;
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}
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unsigned Operand::getIndex() const {
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assert(Index >= 0 && "Index must be set");
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return Index;
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}
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unsigned Operand::getIndex() const { return *Index; }
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bool Operand::isExplicit() const { return Info; }
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@ -53,9 +47,9 @@ bool Operand::isUse() const { return !IsDef; }
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bool Operand::isReg() const { return Tracker; }
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bool Operand::isTied() const { return TiedToIndex >= 0; }
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bool Operand::isTied() const { return TiedToIndex.hasValue(); }
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bool Operand::isVariable() const { return VariableIndex >= 0; }
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bool Operand::isVariable() const { return VariableIndex.hasValue(); }
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bool Operand::isMemory() const {
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return isExplicit() &&
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@ -67,17 +61,9 @@ bool Operand::isImmediate() const {
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getExplicitOperandInfo().OperandType == MCOI::OPERAND_IMMEDIATE;
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}
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unsigned Operand::getTiedToIndex() const {
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assert(isTied() && "Operand must be tied to get the tied index");
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assert(TiedToIndex >= 0 && "TiedToIndex must be set");
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return TiedToIndex;
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}
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unsigned Operand::getTiedToIndex() const { return *TiedToIndex; }
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unsigned Operand::getVariableIndex() const {
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assert(isVariable() && "Operand must be variable to get the Variable index");
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assert(VariableIndex >= 0 && "VariableIndex must be set");
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return VariableIndex;
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}
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unsigned Operand::getVariableIndex() const { return *VariableIndex; }
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unsigned Operand::getImplicitReg() const {
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assert(ImplicitReg);
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@ -94,11 +80,36 @@ const MCOperandInfo &Operand::getExplicitOperandInfo() const {
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return *Info;
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}
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Instruction::Instruction(const MCInstrInfo &InstrInfo,
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const RegisterAliasingTrackerCache &RATC,
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unsigned Opcode)
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: Description(&InstrInfo.get(Opcode)), Name(InstrInfo.getName(Opcode)) {
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const BitVector *BitVectorCache::getUnique(BitVector &&BV) const {
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for (const auto &Entry : Cache)
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if (*Entry == BV)
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return Entry.get();
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Cache.push_back(std::make_unique<BitVector>());
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auto &Entry = Cache.back();
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Entry->swap(BV);
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return Entry.get();
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}
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Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
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SmallVector<Operand, 8> Operands,
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SmallVector<Variable, 4> Variables,
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const BitVector *ImplDefRegs,
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const BitVector *ImplUseRegs,
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const BitVector *AllDefRegs,
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const BitVector *AllUseRegs)
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: Description(*Description), Name(Name), Operands(std::move(Operands)),
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Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
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ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
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AllUseRegs(*AllUseRegs) {}
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std::unique_ptr<Instruction>
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Instruction::create(const MCInstrInfo &InstrInfo,
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const RegisterAliasingTrackerCache &RATC,
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const BitVectorCache &BVC, unsigned Opcode) {
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const llvm::MCInstrDesc *const Description = &InstrInfo.get(Opcode);
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unsigned OpIndex = 0;
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SmallVector<Operand, 8> Operands;
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SmallVector<Variable, 4> Variables;
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for (; OpIndex < Description->getNumOperands(); ++OpIndex) {
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const auto &OpInfo = Description->opInfo_begin()[OpIndex];
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Operand Operand;
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@ -107,8 +118,11 @@ Instruction::Instruction(const MCInstrInfo &InstrInfo,
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// TODO(gchatelet): Handle isLookupPtrRegClass.
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if (OpInfo.RegClass >= 0)
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Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
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Operand.TiedToIndex =
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Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
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int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
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assert(TiedToIndex == -1 ||
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TiedToIndex < std::numeric_limits<uint8_t>::max());
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if (TiedToIndex >= 0)
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Operand.TiedToIndex = TiedToIndex;
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Operand.Info = &OpInfo;
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Operands.push_back(Operand);
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}
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@ -130,28 +144,29 @@ Instruction::Instruction(const MCInstrInfo &InstrInfo,
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Operand.ImplicitReg = MCPhysReg;
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Operands.push_back(Operand);
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}
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// Assigning Variables to non tied explicit operands.
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Variables.reserve(Operands.size()); // Variables.size() <= Operands.size()
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// Assigning Variables to non tied explicit operands.
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for (auto &Op : Operands)
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if (Op.isExplicit() && !Op.isTied()) {
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const size_t VariableIndex = Variables.size();
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assert(VariableIndex < std::numeric_limits<uint8_t>::max());
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Op.VariableIndex = VariableIndex;
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Variables.emplace_back();
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Variables.back().Index = VariableIndex;
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}
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// Assigning Variables to tied operands.
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for (auto &Op : Operands)
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if (Op.isTied())
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if (Op.isExplicit() && Op.isTied())
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Op.VariableIndex = Operands[Op.getTiedToIndex()].getVariableIndex();
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// Assigning Operands to Variables.
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for (auto &Op : Operands)
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if (Op.isVariable())
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Variables[Op.getVariableIndex()].TiedOperands.push_back(Op.getIndex());
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// Processing Aliasing.
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ImplDefRegs = RATC.emptyRegisters();
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ImplUseRegs = RATC.emptyRegisters();
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AllDefRegs = RATC.emptyRegisters();
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AllUseRegs = RATC.emptyRegisters();
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BitVector ImplDefRegs = RATC.emptyRegisters();
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BitVector ImplUseRegs = RATC.emptyRegisters();
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BitVector AllDefRegs = RATC.emptyRegisters();
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BitVector AllUseRegs = RATC.emptyRegisters();
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for (const auto &Op : Operands) {
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if (Op.isReg()) {
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const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
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@ -165,6 +180,13 @@ Instruction::Instruction(const MCInstrInfo &InstrInfo,
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ImplUseRegs |= AliasingBits;
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}
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}
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// Can't use make_unique because constructor is private.
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return std::unique_ptr<Instruction>(new Instruction(
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Description, InstrInfo.getName(Opcode), std::move(Operands),
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std::move(Variables), BVC.getUnique(std::move(ImplDefRegs)),
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BVC.getUnique(std::move(ImplUseRegs)),
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BVC.getUnique(std::move(AllDefRegs)),
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BVC.getUnique(std::move(AllUseRegs))));
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}
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const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
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@ -284,7 +306,7 @@ InstructionsCache::InstructionsCache(const MCInstrInfo &InstrInfo,
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const Instruction &InstructionsCache::getInstr(unsigned Opcode) const {
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auto &Found = Instructions[Opcode];
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if (!Found)
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Found.reset(new Instruction(InstrInfo, RATC, Opcode));
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Found = Instruction::create(InstrInfo, RATC, BVC, Opcode);
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return *Found;
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}
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@ -18,6 +18,7 @@
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#ifndef LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
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#define LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
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#include <memory>
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#include <random>
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#include <unordered_map>
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@ -48,7 +49,7 @@ struct Variable {
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// The index of this Variable in Instruction.Variables and its associated
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// Value in InstructionBuilder.VariableValues.
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int Index = -1;
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Optional<uint8_t> Index;
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};
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// MCOperandInfo can only represents Explicit operands. This object gives a
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@ -81,20 +82,40 @@ struct Operand {
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const MCOperandInfo &getExplicitOperandInfo() const;
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// Please use the accessors above and not the following fields.
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int Index = -1;
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Optional<uint8_t> Index;
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bool IsDef = false;
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const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
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const MCOperandInfo *Info = nullptr; // Set for Explicit Op.
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int TiedToIndex = -1; // Set for Reg&Explicit Op.
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Optional<uint8_t> TiedToIndex; // Set for Reg&Explicit Op.
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const MCPhysReg *ImplicitReg = nullptr; // Set for Implicit Op.
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int VariableIndex = -1; // Set for Explicit Op.
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Optional<uint8_t> VariableIndex; // Set for Explicit Op.
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};
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/// A cache of BitVector to reuse between Instructions.
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/// The cache will only be exercised during Instruction initialization.
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/// For X86, this is ~160 unique vectors for all of the ~15K Instructions.
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struct BitVectorCache {
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// Finds or allocates the provided BitVector in the cache and retrieves it's
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// unique instance.
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const BitVector *getUnique(BitVector &&BV) const;
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private:
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mutable std::vector<std::unique_ptr<BitVector>> Cache;
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};
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// A view over an MCInstrDesc offering a convenient interface to compute
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// Register aliasing.
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struct Instruction {
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Instruction(const MCInstrInfo &InstrInfo,
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const RegisterAliasingTrackerCache &RATC, unsigned Opcode);
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// Create an instruction for a particular Opcode.
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static std::unique_ptr<Instruction>
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create(const MCInstrInfo &InstrInfo, const RegisterAliasingTrackerCache &RATC,
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const BitVectorCache &BVC, unsigned Opcode);
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// Prevent copy or move, instructions are allocated once and cached.
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Instruction(const Instruction &) = delete;
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Instruction(Instruction &&) = delete;
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Instruction &operator=(const Instruction &) = delete;
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Instruction &operator=(Instruction &&) = delete;
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// Returns the Operand linked to this Variable.
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// In case the Variable is tied, the primary (i.e. Def) Operand is returned.
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@ -133,14 +154,20 @@ struct Instruction {
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const RegisterAliasingTrackerCache &RATC,
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raw_ostream &Stream) const;
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const MCInstrDesc *Description; // Never nullptr.
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StringRef Name; // The name of this instruction.
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SmallVector<Operand, 8> Operands;
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SmallVector<Variable, 4> Variables;
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BitVector ImplDefRegs; // The set of aliased implicit def registers.
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BitVector ImplUseRegs; // The set of aliased implicit use registers.
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BitVector AllDefRegs; // The set of all aliased def registers.
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BitVector AllUseRegs; // The set of all aliased use registers.
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const MCInstrDesc &Description;
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const StringRef Name; // The name of this instruction.
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const SmallVector<Operand, 8> Operands;
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const SmallVector<Variable, 4> Variables;
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const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
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const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
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const BitVector &AllDefRegs; // The set of all aliased def registers.
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const BitVector &AllUseRegs; // The set of all aliased use registers.
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private:
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Instruction(const MCInstrDesc *Description, StringRef Name,
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SmallVector<Operand, 8> Operands,
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SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
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const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
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const BitVector *AllUseRegs);
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};
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// Instructions are expensive to instantiate. This class provides a cache of
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@ -157,6 +184,7 @@ private:
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const RegisterAliasingTrackerCache &RATC;
|
||||
mutable std::unordered_map<unsigned, std::unique_ptr<Instruction>>
|
||||
Instructions;
|
||||
const BitVectorCache BVC;
|
||||
};
|
||||
|
||||
// Represents the assignment of a Register to an Operand.
|
||||
|
||||
@ -112,7 +112,7 @@ std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues(
|
||||
return 0;
|
||||
};
|
||||
// Collect used registers that have never been def'ed.
|
||||
for (const Operand &Op : IT.Instr.Operands) {
|
||||
for (const Operand &Op : IT.getInstr().Operands) {
|
||||
if (Op.isUse()) {
|
||||
const unsigned Reg = GetOpReg(Op);
|
||||
if (Reg > 0 && !DefinedRegs.test(Reg)) {
|
||||
@ -122,7 +122,7 @@ std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues(
|
||||
}
|
||||
}
|
||||
// Mark defs as having been def'ed.
|
||||
for (const Operand &Op : IT.Instr.Operands) {
|
||||
for (const Operand &Op : IT.getInstr().Operands) {
|
||||
if (Op.isDef()) {
|
||||
const unsigned Reg = GetOpReg(Op);
|
||||
if (Reg > 0)
|
||||
@ -141,7 +141,7 @@ generateSelfAliasingCodeTemplates(const Instruction &Instr) {
|
||||
std::vector<CodeTemplate> Result;
|
||||
Result.emplace_back();
|
||||
CodeTemplate &CT = Result.back();
|
||||
InstructionTemplate IT(Instr);
|
||||
InstructionTemplate IT(&Instr);
|
||||
if (SelfAliasing.hasImplicitAliasing()) {
|
||||
CT.Info = "implicit Self cycles, picking random values.";
|
||||
} else {
|
||||
@ -160,7 +160,7 @@ generateUnconstrainedCodeTemplates(const Instruction &Instr, StringRef Msg) {
|
||||
Result.emplace_back();
|
||||
CodeTemplate &CT = Result.back();
|
||||
CT.Info = formatv("{0}, repeating an unconstrained assignment", Msg);
|
||||
CT.Instructions.emplace_back(Instr);
|
||||
CT.Instructions.emplace_back(&Instr);
|
||||
return std::move(Result);
|
||||
}
|
||||
|
||||
@ -218,10 +218,11 @@ void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
|
||||
void randomizeUnsetVariables(const ExegesisTarget &Target,
|
||||
const BitVector &ForbiddenRegs,
|
||||
InstructionTemplate &IT) {
|
||||
for (const Variable &Var : IT.Instr.Variables) {
|
||||
for (const Variable &Var : IT.getInstr().Variables) {
|
||||
MCOperand &AssignedValue = IT.getValueFor(Var);
|
||||
if (!AssignedValue.isValid())
|
||||
Target.randomizeMCOperand(IT.Instr, Var, AssignedValue, ForbiddenRegs);
|
||||
Target.randomizeMCOperand(IT.getInstr(), Var, AssignedValue,
|
||||
ForbiddenRegs);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -127,7 +127,7 @@ static std::vector<InstructionTemplate> generateSnippetUsingStaticRenaming(
|
||||
std::vector<BitVector> PossibleRegsForVar;
|
||||
for (const Variable *Var : TiedVariables) {
|
||||
assert(Var);
|
||||
const Operand &Op = IT.Instr.getPrimaryOperand(*Var);
|
||||
const Operand &Op = IT.getInstr().getPrimaryOperand(*Var);
|
||||
assert(Op.isReg());
|
||||
BitVector PossibleRegs = Op.getRegisterAliasing().sourceBits();
|
||||
remove(PossibleRegs, ForbiddenRegisters);
|
||||
@ -166,7 +166,7 @@ Expected<std::vector<CodeTemplate>> UopsSnippetGenerator::generateCodeTemplates(
|
||||
State.getTargetMachine().getTargetTriple())
|
||||
: 0;
|
||||
const AliasingConfigurations SelfAliasing(Instr, Instr);
|
||||
InstructionTemplate IT(Instr);
|
||||
InstructionTemplate IT(&Instr);
|
||||
if (SelfAliasing.empty()) {
|
||||
CT.Info = "instruction is parallel, repeating a random one.";
|
||||
CT.Instructions.push_back(std::move(IT));
|
||||
|
||||
@ -25,7 +25,7 @@ namespace exegesis {
|
||||
// Returns an error if we cannot handle the memory references in this
|
||||
// instruction.
|
||||
static Error isInvalidMemoryInstr(const Instruction &Instr) {
|
||||
switch (Instr.Description->TSFlags & X86II::FormMask) {
|
||||
switch (Instr.Description.TSFlags & X86II::FormMask) {
|
||||
default:
|
||||
llvm_unreachable("Unknown FormMask value");
|
||||
// These have no memory access.
|
||||
@ -114,10 +114,10 @@ static Error isInvalidMemoryInstr(const Instruction &Instr) {
|
||||
case X86II::RawFrmImm8:
|
||||
return Error::success();
|
||||
case X86II::AddRegFrm:
|
||||
return (Instr.Description->Opcode == X86::POP16r ||
|
||||
Instr.Description->Opcode == X86::POP32r ||
|
||||
Instr.Description->Opcode == X86::PUSH16r ||
|
||||
Instr.Description->Opcode == X86::PUSH32r)
|
||||
return (Instr.Description.Opcode == X86::POP16r ||
|
||||
Instr.Description.Opcode == X86::POP32r ||
|
||||
Instr.Description.Opcode == X86::PUSH16r ||
|
||||
Instr.Description.Opcode == X86::PUSH32r)
|
||||
? make_error<Failure>(
|
||||
"unsupported opcode: unsupported memory access")
|
||||
: Error::success();
|
||||
@ -150,7 +150,7 @@ static Error isInvalidMemoryInstr(const Instruction &Instr) {
|
||||
|
||||
static Error IsInvalidOpcode(const Instruction &Instr) {
|
||||
const auto OpcodeName = Instr.Name;
|
||||
if ((Instr.Description->TSFlags & X86II::FormMask) == X86II::Pseudo)
|
||||
if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
|
||||
return make_error<Failure>("unsupported opcode: pseudo instruction");
|
||||
if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
|
||||
OpcodeName.startswith("ADJCALLSTACK"))
|
||||
@ -172,13 +172,13 @@ static Error IsInvalidOpcode(const Instruction &Instr) {
|
||||
}
|
||||
|
||||
static unsigned getX86FPFlags(const Instruction &Instr) {
|
||||
return Instr.Description->TSFlags & X86II::FPTypeMask;
|
||||
return Instr.Description.TSFlags & X86II::FPTypeMask;
|
||||
}
|
||||
|
||||
// Helper to fill a memory operand with a value.
|
||||
static void setMemOp(InstructionTemplate &IT, int OpIdx,
|
||||
const MCOperand &OpVal) {
|
||||
const auto Op = IT.Instr.Operands[OpIdx];
|
||||
const auto Op = IT.getInstr().Operands[OpIdx];
|
||||
assert(Op.isExplicit() && "invalid memory pattern");
|
||||
IT.getValueFor(Op) = OpVal;
|
||||
}
|
||||
@ -190,7 +190,7 @@ static Expected<std::vector<CodeTemplate>> generateLEATemplatesCommon(
|
||||
const LLVMState &State, const SnippetGenerator::Options &Opts,
|
||||
std::function<unsigned(unsigned, unsigned)> GetDestReg) {
|
||||
assert(Instr.Operands.size() == 6 && "invalid LEA");
|
||||
assert(X86II::getMemoryOperandNo(Instr.Description->TSFlags) == 1 &&
|
||||
assert(X86II::getMemoryOperandNo(Instr.Description.TSFlags) == 1 &&
|
||||
"invalid LEA");
|
||||
|
||||
constexpr const int kDestOp = 0;
|
||||
@ -213,7 +213,7 @@ static Expected<std::vector<CodeTemplate>> generateLEATemplatesCommon(
|
||||
for (int LogScale = 0; LogScale <= 3; ++LogScale) {
|
||||
// FIXME: Add an option for controlling how we explore immediates.
|
||||
for (const int Disp : {0, 42}) {
|
||||
InstructionTemplate IT(Instr);
|
||||
InstructionTemplate IT(&Instr);
|
||||
const int64_t Scale = 1ull << LogScale;
|
||||
setMemOp(IT, 1, MCOperand::createReg(BaseReg));
|
||||
setMemOp(IT, 2, MCOperand::createImm(Scale));
|
||||
@ -259,7 +259,7 @@ X86LatencySnippetGenerator::generateCodeTemplates(
|
||||
return std::move(E);
|
||||
|
||||
// LEA gets special attention.
|
||||
const auto Opcode = Instr.Description->getOpcode();
|
||||
const auto Opcode = Instr.Description.getOpcode();
|
||||
if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
|
||||
return generateLEATemplatesCommon(Instr, ForbiddenRegisters, State, Opts,
|
||||
[](unsigned BaseReg, unsigned IndexReg) {
|
||||
@ -310,7 +310,7 @@ X86UopsSnippetGenerator::generateCodeTemplates(
|
||||
return std::move(E);
|
||||
|
||||
// LEA gets special attention.
|
||||
const auto Opcode = Instr.Description->getOpcode();
|
||||
const auto Opcode = Instr.Description.getOpcode();
|
||||
if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
|
||||
// Any destination register that is not used for adddressing is fine.
|
||||
auto PossibleDestRegs =
|
||||
@ -648,13 +648,13 @@ void ExegesisX86Target::randomizeMCOperand(
|
||||
void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
|
||||
unsigned Reg,
|
||||
unsigned Offset) const {
|
||||
assert(!isInvalidMemoryInstr(IT.Instr) &&
|
||||
assert(!isInvalidMemoryInstr(IT.getInstr()) &&
|
||||
"fillMemoryOperands requires a valid memory instruction");
|
||||
int MemOpIdx = X86II::getMemoryOperandNo(IT.Instr.Description->TSFlags);
|
||||
int MemOpIdx = X86II::getMemoryOperandNo(IT.getInstr().Description.TSFlags);
|
||||
assert(MemOpIdx >= 0 && "invalid memory operand index");
|
||||
// getMemoryOperandNo() ignores tied operands, so we have to add them back.
|
||||
for (unsigned I = 0; I <= static_cast<unsigned>(MemOpIdx); ++I) {
|
||||
const auto &Op = IT.Instr.Operands[I];
|
||||
const auto &Op = IT.getInstr().Operands[I];
|
||||
if (Op.isTied() && Op.getTiedToIndex() < I) {
|
||||
++MemOpIdx;
|
||||
}
|
||||
|
||||
@ -208,7 +208,7 @@ static Expected<std::vector<BenchmarkCode>>
|
||||
generateSnippets(const LLVMState &State, unsigned Opcode,
|
||||
const BitVector &ForbiddenRegs) {
|
||||
const Instruction &Instr = State.getIC().getInstr(Opcode);
|
||||
const MCInstrDesc &InstrDesc = *Instr.Description;
|
||||
const MCInstrDesc &InstrDesc = Instr.Description;
|
||||
// Ignore instructions that we cannot run.
|
||||
if (InstrDesc.isPseudo())
|
||||
return make_error<Failure>("Unsupported opcode: isPseudo");
|
||||
|
||||
@ -81,8 +81,8 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(3));
|
||||
EXPECT_THAT(IT.VariableValues,
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
|
||||
EXPECT_THAT(IT.getVariableValues(),
|
||||
AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
|
||||
ElementsAre(IsReg(), IsReg(), IsInvalid())))
|
||||
<< "Op0 is either set to Op1 or to Op2";
|
||||
|
||||
@ -86,8 +86,8 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(1)); // Imm.
|
||||
EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Immediate is not set";
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
|
||||
EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
|
||||
}
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
|
||||
@ -109,9 +109,9 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(2));
|
||||
EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Operand 1 is not set";
|
||||
EXPECT_THAT(IT.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
|
||||
EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
|
||||
EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
|
||||
}
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
|
||||
@ -131,8 +131,8 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(3));
|
||||
EXPECT_THAT(IT.VariableValues,
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
|
||||
EXPECT_THAT(IT.getVariableValues(),
|
||||
AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
|
||||
ElementsAre(IsReg(), IsReg(), IsInvalid())))
|
||||
<< "Op0 is either set to Op1 or to Op2";
|
||||
@ -173,9 +173,10 @@ TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(2));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(2));
|
||||
EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
|
||||
ElementsAre(IsInvalid(), IsReg())));
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
|
||||
EXPECT_THAT(IT.getVariableValues(),
|
||||
AnyOf(ElementsAre(IsReg(), IsInvalid()),
|
||||
ElementsAre(IsInvalid(), IsReg())));
|
||||
EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
|
||||
// TODO: check that the two instructions alias each other.
|
||||
}
|
||||
@ -193,7 +194,7 @@ TEST_F(LatencySnippetGeneratorTest, LAHF) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(2));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(0));
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
|
||||
}
|
||||
}
|
||||
|
||||
@ -212,9 +213,9 @@ TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(2));
|
||||
EXPECT_THAT(IT.VariableValues[0], IsInvalid());
|
||||
EXPECT_THAT(IT.VariableValues[1], IsInvalid());
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
|
||||
EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
|
||||
EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
|
||||
}
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
|
||||
@ -233,7 +234,7 @@ TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(0));
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
|
||||
}
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
|
||||
@ -260,8 +261,8 @@ TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
|
||||
std::unordered_set<unsigned> AllDefRegisters;
|
||||
for (const auto &IT : CT.Instructions) {
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(3));
|
||||
AllDefRegisters.insert(IT.VariableValues[0].getReg());
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
|
||||
AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
|
||||
}
|
||||
EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
|
||||
<< "Each instruction writes to a different register";
|
||||
@ -291,12 +292,14 @@ TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(4));
|
||||
EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[1].getReg()))
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
|
||||
EXPECT_THAT(IT.getVariableValues()[0].getReg(),
|
||||
Not(IT.getVariableValues()[1].getReg()))
|
||||
<< "Def is different from first Use";
|
||||
EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[2].getReg()))
|
||||
EXPECT_THAT(IT.getVariableValues()[0].getReg(),
|
||||
Not(IT.getVariableValues()[2].getReg()))
|
||||
<< "Def is different from second Use";
|
||||
EXPECT_THAT(IT.VariableValues[3], IsInvalid());
|
||||
EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
|
||||
}
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
|
||||
@ -326,11 +329,11 @@ TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
|
||||
SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(6));
|
||||
EXPECT_EQ(IT.VariableValues[2].getImm(), 1);
|
||||
EXPECT_EQ(IT.VariableValues[3].getReg(), 0u);
|
||||
EXPECT_EQ(IT.VariableValues[4].getImm(), 0);
|
||||
EXPECT_EQ(IT.VariableValues[5].getReg(), 0u);
|
||||
ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
|
||||
EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
|
||||
EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
|
||||
EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
|
||||
EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
|
||||
}
|
||||
|
||||
class FakeSnippetGenerator : public SnippetGenerator {
|
||||
@ -338,10 +341,14 @@ public:
|
||||
FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
|
||||
: SnippetGenerator(State, Opts) {}
|
||||
|
||||
Instruction createInstruction(unsigned Opcode) {
|
||||
const Instruction &getInstr(unsigned Opcode) {
|
||||
return State.getIC().getInstr(Opcode);
|
||||
}
|
||||
|
||||
InstructionTemplate getInstructionTemplate(unsigned Opcode) {
|
||||
return {&getInstr(Opcode)};
|
||||
}
|
||||
|
||||
private:
|
||||
Expected<std::vector<CodeTemplate>>
|
||||
generateCodeTemplates(const Instruction &, const BitVector &) const override {
|
||||
@ -389,8 +396,8 @@ TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
|
||||
// explicit use 1 : reg RegClass=GR16 | TIED_TO:0
|
||||
// explicit use 2 : imm
|
||||
// implicit def : EFLAGS
|
||||
InstructionTemplate IT(Generator.createInstruction(X86::ADD16ri));
|
||||
IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX);
|
||||
InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
|
||||
IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
|
||||
std::vector<InstructionTemplate> Snippet;
|
||||
Snippet.push_back(std::move(IT));
|
||||
const auto RIV = Generator.computeRegisterInitialValues(Snippet);
|
||||
@ -404,15 +411,18 @@ TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
|
||||
// -> only rbx needs defining.
|
||||
std::vector<InstructionTemplate> Snippet;
|
||||
{
|
||||
InstructionTemplate Mov(Generator.createInstruction(X86::MOV64ri));
|
||||
Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
|
||||
Mov.getValueFor(Mov.Instr.Variables[1]) = MCOperand::createImm(42);
|
||||
InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
|
||||
Mov.getValueFor(Mov.getInstr().Variables[0]) =
|
||||
MCOperand::createReg(X86::RAX);
|
||||
Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
|
||||
Snippet.push_back(std::move(Mov));
|
||||
}
|
||||
{
|
||||
InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr));
|
||||
Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
|
||||
Add.getValueFor(Add.Instr.Variables[1]) = MCOperand::createReg(X86::RBX);
|
||||
InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
|
||||
Add.getValueFor(Add.getInstr().Variables[0]) =
|
||||
MCOperand::createReg(X86::RAX);
|
||||
Add.getValueFor(Add.getInstr().Variables[1]) =
|
||||
MCOperand::createReg(X86::RBX);
|
||||
Snippet.push_back(std::move(Add));
|
||||
}
|
||||
|
||||
|
||||
@ -119,6 +119,10 @@ protected:
|
||||
Value);
|
||||
}
|
||||
|
||||
const Instruction &getInstr(unsigned OpCode) {
|
||||
return State.getIC().getInstr(OpCode);
|
||||
}
|
||||
|
||||
LLVMState State;
|
||||
};
|
||||
|
||||
@ -355,8 +359,8 @@ TEST_F(Core2TargetTest, SetRegToFP1_4Bits) {
|
||||
}
|
||||
|
||||
TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
|
||||
Instruction I(State.getInstrInfo(), State.getRATC(), X86::ADD64rm);
|
||||
InstructionTemplate IT(I);
|
||||
const Instruction &I = getInstr(X86::ADD64rm);
|
||||
InstructionTemplate IT(&I);
|
||||
constexpr const int kOffset = 42;
|
||||
State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
|
||||
// Memory is operands 2-6.
|
||||
@ -368,8 +372,8 @@ TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
|
||||
}
|
||||
|
||||
TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
|
||||
Instruction I(State.getInstrInfo(), State.getRATC(), X86::VGATHERDPSZ128rm);
|
||||
InstructionTemplate IT(I);
|
||||
const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
|
||||
InstructionTemplate IT(&I);
|
||||
constexpr const int kOffset = 42;
|
||||
State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
|
||||
// Memory is operands 4-8.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user