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[MIPS GlobalISel] Fix mul operands
Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355594
This commit is contained in:
Petar Avramovic
parent
16d98c206b
commit
3d3120dc9a
@ -131,10 +131,23 @@ bool MipsInstructionSelector::select(MachineInstr &I,
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return true;
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}
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if (selectImpl(I, CoverageInfo)) {
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if (I.getOpcode() == Mips::G_MUL) {
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MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.add(I.getOperand(2));
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if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
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return false;
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Mul->getOperand(3).setIsDead(true);
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Mul->getOperand(4).setIsDead(true);
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I.eraseFromParent();
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return true;
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}
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if (selectImpl(I, CoverageInfo))
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return true;
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MachineInstr *MI = nullptr;
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using namespace TargetOpcode;
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@ -3,7 +3,7 @@
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--- |
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define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
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...
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---
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@ -20,7 +20,7 @@ body: |
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def $hi0, implicit-def $lo0
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; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
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; MIPS32: $v0 = COPY [[MUL]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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@ -38,13 +38,15 @@ regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $a0, $a1, $a2
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: umul_with_overflow
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
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; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
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; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
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; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
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@ -54,18 +56,22 @@ body: |
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; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
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; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
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; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag)
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; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
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; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
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; MIPS32: RetRA
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%6:gprb(s32) = G_UMULH %0, %1
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%7:gprb(s32) = G_CONSTANT i32 0
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%8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7
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%9:gprb(s32) = G_CONSTANT i32 1
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%10:gprb(s32) = COPY %8(s32)
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%5:gprb(s32) = G_AND %10, %9
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G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
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%3:gprb(p0) = COPY $a3
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%4:gprb(s32) = G_MUL %0, %1
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%7:gprb(s32) = G_UMULH %0, %1
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%8:gprb(s32) = G_CONSTANT i32 0
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%9:gprb(s32) = G_ICMP intpred(ne), %7(s32), %8
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%10:gprb(s32) = G_CONSTANT i32 1
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%11:gprb(s32) = COPY %9(s32)
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%6:gprb(s32) = G_AND %11, %10
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G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
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G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
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RetRA
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...
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@ -9,7 +9,7 @@
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define void @mul_i16_sext() {entry: ret void}
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define void @mul_i16_zext() {entry: ret void}
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define void @mul_i16_aext() {entry: ret void}
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
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...
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---
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@ -218,26 +218,31 @@ alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $a0, $a1, $a2
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: umul_with_overflow
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
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; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
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; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
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; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
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; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
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; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul)
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; MIPS32: RetRA
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(p0) = COPY $a2
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%3:_(s32), %4:_(s1) = G_UMULO %0, %1
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G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag)
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%3:_(p0) = COPY $a3
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%4:_(s32), %5:_(s1) = G_UMULO %0, %1
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G_STORE %5(s1), %3(p0) :: (store 1 into %ir.pcarry_flag)
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G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
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RetRA
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...
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@ -88,9 +88,10 @@ entry:
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}
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declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) {
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; MIPS32-LABEL: umul_with_overflow:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: mul $1, $4, $5
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; MIPS32-NEXT: multu $4, $5
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; MIPS32-NEXT: mfhi $4
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; MIPS32-NEXT: lui $5, 0
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@ -100,11 +101,14 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
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; MIPS32-NEXT: lui $5, 0
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; MIPS32-NEXT: ori $5, $5, 1
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; MIPS32-NEXT: and $4, $4, $5
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; MIPS32-NEXT: sb $4, 0($6)
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; MIPS32-NEXT: sb $4, 0($7)
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; MIPS32-NEXT: sw $1, 0($6)
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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%res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
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%carry_flag = extractvalue { i32, i1 } %res, 1
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%mul = extractvalue { i32, i1 } %res, 0
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store i1 %carry_flag, i1* %pcarry_flag
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store i32 %mul, i32* %pmul
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ret void
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}
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@ -3,7 +3,7 @@
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--- |
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define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
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define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
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...
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---
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@ -36,31 +36,37 @@ legalized: true
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tracksRegLiveness: true
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body: |
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bb.1 (%ir-block.0):
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liveins: $a0, $a1, $a2
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: umul_with_overflow
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
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; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
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; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
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; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
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; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]]
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; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
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; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C1]]
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; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
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; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul)
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; MIPS32: RetRA
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(p0) = COPY $a2
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%6:_(s32) = G_UMULH %0, %1
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%7:_(s32) = G_CONSTANT i32 0
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%8:_(s32) = G_ICMP intpred(ne), %6(s32), %7
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%9:_(s32) = G_CONSTANT i32 1
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%10:_(s32) = COPY %8(s32)
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%5:_(s32) = G_AND %10, %9
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G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
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%3:_(p0) = COPY $a3
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%4:_(s32) = G_MUL %0, %1
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%7:_(s32) = G_UMULH %0, %1
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%8:_(s32) = G_CONSTANT i32 0
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%9:_(s32) = G_ICMP intpred(ne), %7(s32), %8
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%10:_(s32) = G_CONSTANT i32 1
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%11:_(s32) = COPY %9(s32)
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%6:_(s32) = G_AND %11, %10
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G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
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G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
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RetRA
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...
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