[SelectionDAG] Fix illegal widening of scalable-vector loads

The process of widening simple vector loads attempts to use a load of a
wider vector type if the original load is sufficiently aligned to avoid
memory faults.

However this optimization is only legal when performed on fixed-length
vector types. For scalable vector types this is invalid (unless vscale
happens to be 1).

This patch does increase the likelihood of compiler crashes (from
`FindMemType` failing to find a suitable type) but this now better
matches how widening non-simple loads, insufficiently-aligned loads, and
scalable-vector stores are handled.

Patches will be introduced later by which loads and stores can be
widened on targets with support for masked or predicated operations.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D111885

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -5394,7 +5394,8 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
   TypeSize WidthDiff = WidenWidth - LdWidth;
   // Allow wider loads if they are sufficiently aligned to avoid memory faults
   // and if the original load is simple.
-  unsigned LdAlign = (!LD->isSimple()) ? 0 : LD->getAlignment();
+  unsigned LdAlign =
+      (!LD->isSimple() || LdVT.isScalableVector()) ? 0 : LD->getAlignment();
 
   // Find the vector type that can load from.
   EVT NewVT = FindMemType(DAG, TLI, LdWidth.getKnownMinSize(), WidenVT, LdAlign,

llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll

@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+
+; Check that we are able to legalize scalable-vector loads that require widening.
+
+; FIXME: LLVM can't yet widen scalable-vector loads.
+
+define <vscale x 3 x i8> @load_nxv3i8(<vscale x 3 x i8>* %ptr) {
+  %v = load <vscale x 3 x i8>, <vscale x 3 x i8>* %ptr
+  ret <vscale x 3 x i8> %v
+}
+
+define <vscale x 5 x half> @load_nxv5f16(<vscale x 5 x half>* %ptr) {
+  %v = load <vscale x 5 x half>, <vscale x 5 x half>* %ptr
+  ret <vscale x 5 x half> %v
+}

llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll

@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+
+; Check that we are able to legalize scalable-vector stores that require widening.
+
+; FIXME: LLVM can't yet widen scalable-vector stores.
+
+define void @store_nxv3i8(<vscale x 3 x i8> %val, <vscale x 3 x i8>* %ptr) {
+  store <vscale x 3 x i8> %val, <vscale x 3 x i8>* %ptr
+  ret void
+}
+
+define void @store_nxv7f64(<vscale x 7 x double> %val, <vscale x 7 x double>* %ptr) {
+  store <vscale x 7 x double> %val, <vscale x 7 x double>* %ptr
+  ret void
+}