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[X86] Remove mask parameter from vpshufbitqmb intrinsics. Change result to a vXi1 vector.
The input mask can be represented with an AND in IR. Fixes PR40258 llvm-svn: 351028
This commit is contained in:
Craig Topper
parent
2fefe153dd
commit
3f3b8ef442
@ -1312,21 +1312,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// BITALG bits shuffle
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_mask_vpshufbitqmb_128 :
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GCCBuiltin<"__builtin_ia32_vpshufbitqmb128_mask">,
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Intrinsic<[llvm_i16_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_vpshufbitqmb_256 :
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GCCBuiltin<"__builtin_ia32_vpshufbitqmb256_mask">,
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Intrinsic<[llvm_i32_ty],
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[llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_vpshufbitqmb_512 :
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GCCBuiltin<"__builtin_ia32_vpshufbitqmb512_mask">,
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Intrinsic<[llvm_i64_ty],
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[llvm_v64i8_ty, llvm_v64i8_ty, llvm_i64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_vpshufbitqmb_128 :
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Intrinsic<[llvm_v16i1_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
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def int_x86_avx512_vpshufbitqmb_256 :
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Intrinsic<[llvm_v32i1_ty], [llvm_v32i8_ty, llvm_v32i8_ty], [IntrNoMem]>;
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def int_x86_avx512_vpshufbitqmb_512 :
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Intrinsic<[llvm_v64i1_ty], [llvm_v64i8_ty, llvm_v64i8_ty], [IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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@ -298,6 +298,7 @@ static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
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Name.startswith("avx512.mask.max.p") || // Added in 7.0. 128/256 in 5.0
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Name.startswith("avx512.mask.min.p") || // Added in 7.0. 128/256 in 5.0
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Name.startswith("avx512.mask.fpclass.p") || // Added in 7.0
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Name.startswith("avx512.mask.vpshufbitqmb.") || // Added in 8.0
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Name == "sse.cvtsi2ss" || // Added in 7.0
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Name == "sse.cvtsi642ss" || // Added in 7.0
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Name == "sse2.cvtsi2sd" || // Added in 7.0
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@ -1758,6 +1759,20 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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// "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt."
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bool CmpEq = Name[16] == 'e';
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Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true);
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} else if (IsX86 && Name.startswith("avx512.mask.vpshufbitqmb.")) {
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Type *OpTy = CI->getArgOperand(0)->getType();
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unsigned VecWidth = OpTy->getPrimitiveSizeInBits();
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Intrinsic::ID IID;
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switch (VecWidth) {
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default: llvm_unreachable("Unexpected intrinsic");
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case 128: IID = Intrinsic::x86_avx512_vpshufbitqmb_128; break;
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case 256: IID = Intrinsic::x86_avx512_vpshufbitqmb_256; break;
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case 512: IID = Intrinsic::x86_avx512_vpshufbitqmb_512; break;
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}
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Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
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{ CI->getOperand(0), CI->getArgOperand(1) });
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Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2));
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} else if (IsX86 && Name.startswith("avx512.mask.fpclass.p")) {
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Type *OpTy = CI->getArgOperand(0)->getType();
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unsigned VecWidth = OpTy->getPrimitiveSizeInBits();
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@ -21378,14 +21378,6 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
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SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
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switch (Op.getOpcode()) {
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default: break;
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case X86ISD::CMPM:
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case X86ISD::CMPM_RND:
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case X86ISD::VPSHUFBITQMB:
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case X86ISD::VFPCLASS:
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return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
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}
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if (PreservedSrc.isUndef())
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PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
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return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
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@ -21841,32 +21833,6 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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FPclassMask, DAG.getIntPtrConstant(0, dl));
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return DAG.getBitcast(MVT::i8, Ins);
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}
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case CMP_MASK: {
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// Comparison intrinsics with masks.
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// Example of transformation:
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// (i8 (int_x86_avx512_mask_pcmpeq_q_128
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// (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
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// (i8 (bitcast
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// (v8i1 (insert_subvector zero,
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// (v2i1 (and (PCMPEQM %a, %b),
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// (extract_subvector
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// (v8i1 (bitcast %mask)), 0))), 0))))
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MVT VT = Op.getOperand(1).getSimpleValueType();
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MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
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SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
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MVT BitcastVT = MVT::getVectorVT(MVT::i1,
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Mask.getSimpleValueType().getSizeInBits());
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SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
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Op.getOperand(2));
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SDValue CmpMask = getVectorMaskingNode(Cmp, Mask, SDValue(),
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Subtarget, DAG);
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// Need to fill with zeros to ensure the bitcast will produce zeroes
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// for the upper bits in the v2i1/v4i1 case.
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SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
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DAG.getConstant(0, dl, BitcastVT),
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CmpMask, DAG.getIntPtrConstant(0, dl));
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return DAG.getBitcast(Op.getValueType(), Res);
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}
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case CMP_MASK_CC: {
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MVT MaskVT = Op.getSimpleValueType();
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@ -23,7 +23,7 @@ enum IntrinsicType : uint16_t {
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GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, XGETBV, ADX, FPCLASS, FPCLASSS,
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP, INTR_TYPE_4OP,
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INTR_TYPE_2OP_IMM8, INTR_TYPE_3OP_IMM8,
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CMP_MASK, CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM,
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CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM,
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CVTPD2PS, CVTPD2PS_MASK, CVTPD2PS_RND_MASK,
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INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
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INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
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@ -845,13 +845,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_512, CVTPS2PH_MASK,
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X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH),
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X86_INTRINSIC_DATA(avx512_mask_vpshufbitqmb_128, CMP_MASK,
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X86ISD::VPSHUFBITQMB, 0),
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X86_INTRINSIC_DATA(avx512_mask_vpshufbitqmb_256, CMP_MASK,
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X86ISD::VPSHUFBITQMB, 0),
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X86_INTRINSIC_DATA(avx512_mask_vpshufbitqmb_512, CMP_MASK,
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X86ISD::VPSHUFBITQMB, 0),
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X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_128, FIXUPIMM_MASKZ,
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X86ISD::VFIXUPIMM, 0),
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X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_256, FIXUPIMM_MASKZ,
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@ -1029,6 +1022,9 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_vpmadd52l_uq_128 , IFMA_OP, X86ISD::VPMADD52L, 0),
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X86_INTRINSIC_DATA(avx512_vpmadd52l_uq_256 , IFMA_OP, X86ISD::VPMADD52L, 0),
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X86_INTRINSIC_DATA(avx512_vpmadd52l_uq_512 , IFMA_OP, X86ISD::VPMADD52L, 0),
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X86_INTRINSIC_DATA(avx512_vpshufbitqmb_128, INTR_TYPE_2OP, X86ISD::VPSHUFBITQMB, 0),
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X86_INTRINSIC_DATA(avx512_vpshufbitqmb_256, INTR_TYPE_2OP, X86ISD::VPSHUFBITQMB, 0),
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X86_INTRINSIC_DATA(avx512_vpshufbitqmb_512, INTR_TYPE_2OP, X86ISD::VPSHUFBITQMB, 0),
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X86_INTRINSIC_DATA(bmi_bextr_32, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
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X86_INTRINSIC_DATA(bmi_bextr_64, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
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X86_INTRINSIC_DATA(bmi_bzhi_32, INTR_TYPE_2OP, X86ISD::BZHI, 0),
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@ -1,41 +1,51 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512bitalg,+avx512vl | FileCheck %s
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declare i16 @llvm.x86.avx512.mask.vpshufbitqmb.128(<16 x i8> %a, <16 x i8> %b, i16 %mask)
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define i16 @test_vpshufbitqmb_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) {
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define i16 @test_vpshufbitqmb_128(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
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; CHECK-LABEL: test_vpshufbitqmb_128:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: kmovd %edi, %k1
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; CHECK-NEXT: vpshufbitqmb %xmm1, %xmm0, %k0 {%k1}
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; CHECK-NEXT: vpshufbitqmb %xmm1, %xmm0, %k1
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; CHECK-NEXT: vpshufbitqmb %xmm3, %xmm2, %k0 {%k1}
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; CHECK-NEXT: kmovd %k0, %eax
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; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%res = call i16 @llvm.x86.avx512.mask.vpshufbitqmb.128(<16 x i8> %a, <16 x i8> %b, i16 %mask)
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ret i16 %res
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%tmp = call <16 x i1> @llvm.x86.avx512.vpshufbitqmb.128(<16 x i8> %a, <16 x i8> %b)
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%tmp1 = call <16 x i1> @llvm.x86.avx512.vpshufbitqmb.128(<16 x i8> %c, <16 x i8> %d)
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%tmp2 = and <16 x i1> %tmp, %tmp1
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%tmp3 = bitcast <16 x i1> %tmp2 to i16
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ret i16 %tmp3
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}
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declare i32 @llvm.x86.avx512.mask.vpshufbitqmb.256(<32 x i8> %a, <32 x i8> %b, i32 %mask)
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define i32 @test_vpshufbitqmb_256(<32 x i8> %a, <32 x i8> %b, i32 %mask) {
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define i32 @test_vpshufbitqmb_256(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i8> %d) {
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; CHECK-LABEL: test_vpshufbitqmb_256:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: kmovd %edi, %k1
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; CHECK-NEXT: vpshufbitqmb %ymm1, %ymm0, %k0 {%k1}
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; CHECK-NEXT: vpshufbitqmb %ymm1, %ymm0, %k1
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; CHECK-NEXT: vpshufbitqmb %ymm3, %ymm2, %k0 {%k1}
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; CHECK-NEXT: kmovd %k0, %eax
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%res = call i32 @llvm.x86.avx512.mask.vpshufbitqmb.256(<32 x i8> %a, <32 x i8> %b, i32 %mask)
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ret i32 %res
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%tmp = call <32 x i1> @llvm.x86.avx512.vpshufbitqmb.256(<32 x i8> %a, <32 x i8> %b)
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%tmp1 = call <32 x i1> @llvm.x86.avx512.vpshufbitqmb.256(<32 x i8> %c, <32 x i8> %d)
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%tmp2 = and <32 x i1> %tmp, %tmp1
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%tmp3 = bitcast <32 x i1> %tmp2 to i32
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ret i32 %tmp3
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}
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declare i64 @llvm.x86.avx512.mask.vpshufbitqmb.512(<64 x i8> %a, <64 x i8> %b, i64 %mask)
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define i64 @test_vpshufbitqmb_512(<64 x i8> %a, <64 x i8> %b, i64 %mask) {
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define i64 @test_vpshufbitqmb_512(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i8> %d) {
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; CHECK-LABEL: test_vpshufbitqmb_512:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: kmovq %rdi, %k1
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; CHECK-NEXT: vpshufbitqmb %zmm1, %zmm0, %k0 {%k1}
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; CHECK-NEXT: vpshufbitqmb %zmm1, %zmm0, %k1
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; CHECK-NEXT: vpshufbitqmb %zmm3, %zmm2, %k0 {%k1}
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; CHECK-NEXT: kmovq %k0, %rax
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%res = call i64 @llvm.x86.avx512.mask.vpshufbitqmb.512(<64 x i8> %a, <64 x i8> %b, i64 %mask)
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ret i64 %res
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%tmp = call <64 x i1> @llvm.x86.avx512.vpshufbitqmb.512(<64 x i8> %a, <64 x i8> %b)
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%tmp1 = call <64 x i1> @llvm.x86.avx512.vpshufbitqmb.512(<64 x i8> %c, <64 x i8> %d)
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%tmp2 = and <64 x i1> %tmp, %tmp1
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%tmp3 = bitcast <64 x i1> %tmp2 to i64
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ret i64 %tmp3
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}
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declare <16 x i1> @llvm.x86.avx512.vpshufbitqmb.128(<16 x i8>, <16 x i8>)
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declare <32 x i1> @llvm.x86.avx512.vpshufbitqmb.256(<32 x i8>, <32 x i8>)
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declare <64 x i1> @llvm.x86.avx512.vpshufbitqmb.512(<64 x i8>, <64 x i8>)
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