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[ARM] and + load combine tests
Adding autogenerated tests for narrow load combines. Differential Revision: https://reviews.llvm.org/D40709 llvm-svn: 319542
This commit is contained in:
Sam Parker
parent
0b58c328d4
commit
412a991b10
674
llvm/test/CodeGen/ARM/and-load-combine.ll
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674
llvm/test/CodeGen/ARM/and-load-combine.ll
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@ -0,0 +1,674 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s --check-prefix=ARM
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; RUN: llc -mtriple=armv7eb %s -o - | FileCheck %s --check-prefix=ARMEB
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; RUN: llc -mtriple=armv6m %s -o - | FileCheck %s --check-prefix=THUMB1
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; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
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define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
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; ARM-LABEL: cmp_xor8_short_short:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldrh r0, [r0]
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; ARM-NEXT: ldrh r1, [r1]
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; ARM-NEXT: eor r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, #255
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_xor8_short_short:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldrh r0, [r0]
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; ARMEB-NEXT: ldrh r1, [r1]
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; ARMEB-NEXT: eor r1, r1, r0
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; ARMEB-NEXT: mov r0, #0
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; ARMEB-NEXT: tst r1, #255
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; ARMEB-NEXT: movweq r0, #1
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; ARMEB-NEXT: bx lr
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;
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; THUMB1-LABEL: cmp_xor8_short_short:
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; THUMB1: @ BB#0: @ %entry
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; THUMB1-NEXT: ldrh r0, [r0]
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; THUMB1-NEXT: ldrh r2, [r1]
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; THUMB1-NEXT: eors r2, r0
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; THUMB1-NEXT: movs r0, #1
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; THUMB1-NEXT: movs r1, #0
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; THUMB1-NEXT: lsls r2, r2, #24
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; THUMB1-NEXT: beq .LBB0_2
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; THUMB1-NEXT: @ BB#1: @ %entry
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; THUMB1-NEXT: mov r0, r1
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; THUMB1-NEXT: .LBB0_2: @ %entry
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; THUMB1-NEXT: bx lr
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;
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; THUMB2-LABEL: cmp_xor8_short_short:
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; THUMB2: @ BB#0: @ %entry
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; THUMB2-NEXT: ldrh r0, [r0]
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; THUMB2-NEXT: ldrh r1, [r1]
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; THUMB2-NEXT: eors r0, r1
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; THUMB2-NEXT: lsls r0, r0, #24
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; THUMB2-NEXT: mov.w r0, #0
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; THUMB2-NEXT: it eq
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; THUMB2-NEXT: moveq r0, #1
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; THUMB2-NEXT: bx lr
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i16* nocapture readonly %b) {
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entry:
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%0 = load i16, i16* %a, align 2
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%1 = load i16, i16* %b, align 2
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%xor2 = xor i16 %1, %0
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%2 = and i16 %xor2, 255
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%cmp = icmp eq i16 %2, 0
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ret i1 %cmp
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}
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define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a,
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; ARM-LABEL: cmp_xor8_short_int:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldrh r0, [r0]
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; ARM-NEXT: ldr r1, [r1]
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; ARM-NEXT: eor r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, #255
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_xor8_short_int:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldrh r0, [r0]
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; ARMEB-NEXT: ldr r1, [r1]
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; ARMEB-NEXT: eor r1, r1, r0
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; ARMEB-NEXT: mov r0, #0
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; ARMEB-NEXT: tst r1, #255
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; ARMEB-NEXT: movweq r0, #1
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; ARMEB-NEXT: bx lr
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;
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; THUMB1-LABEL: cmp_xor8_short_int:
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; THUMB1: @ BB#0: @ %entry
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; THUMB1-NEXT: ldrh r0, [r0]
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; THUMB1-NEXT: ldr r2, [r1]
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; THUMB1-NEXT: eors r2, r0
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; THUMB1-NEXT: movs r0, #1
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; THUMB1-NEXT: movs r1, #0
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; THUMB1-NEXT: lsls r2, r2, #24
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; THUMB1-NEXT: beq .LBB1_2
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; THUMB1-NEXT: @ BB#1: @ %entry
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; THUMB1-NEXT: mov r0, r1
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; THUMB1-NEXT: .LBB1_2: @ %entry
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; THUMB1-NEXT: bx lr
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;
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; THUMB2-LABEL: cmp_xor8_short_int:
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; THUMB2: @ BB#0: @ %entry
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; THUMB2-NEXT: ldrh r0, [r0]
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; THUMB2-NEXT: ldr r1, [r1]
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; THUMB2-NEXT: eors r0, r1
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; THUMB2-NEXT: lsls r0, r0, #24
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; THUMB2-NEXT: mov.w r0, #0
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; THUMB2-NEXT: it eq
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; THUMB2-NEXT: moveq r0, #1
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; THUMB2-NEXT: bx lr
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i32* nocapture readonly %b) {
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entry:
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%0 = load i16, i16* %a, align 2
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%conv = zext i16 %0 to i32
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%1 = load i32, i32* %b, align 4
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%xor = xor i32 %1, %conv
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%and = and i32 %xor, 255
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a,
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; ARM-LABEL: cmp_xor8_int_int:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldr r0, [r0]
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; ARM-NEXT: ldr r1, [r1]
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; ARM-NEXT: eor r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, #255
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_xor8_int_int:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldr r0, [r0]
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; ARMEB-NEXT: ldr r1, [r1]
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; ARMEB-NEXT: eor r1, r1, r0
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; ARMEB-NEXT: mov r0, #0
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; ARMEB-NEXT: tst r1, #255
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; ARMEB-NEXT: movweq r0, #1
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; ARMEB-NEXT: bx lr
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;
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; THUMB1-LABEL: cmp_xor8_int_int:
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; THUMB1: @ BB#0: @ %entry
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; THUMB1-NEXT: ldr r0, [r0]
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; THUMB1-NEXT: ldr r2, [r1]
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; THUMB1-NEXT: eors r2, r0
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; THUMB1-NEXT: movs r0, #1
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; THUMB1-NEXT: movs r1, #0
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; THUMB1-NEXT: lsls r2, r2, #24
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; THUMB1-NEXT: beq .LBB2_2
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; THUMB1-NEXT: @ BB#1: @ %entry
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; THUMB1-NEXT: mov r0, r1
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; THUMB1-NEXT: .LBB2_2: @ %entry
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; THUMB1-NEXT: bx lr
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;
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; THUMB2-LABEL: cmp_xor8_int_int:
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; THUMB2: @ BB#0: @ %entry
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; THUMB2-NEXT: ldr r0, [r0]
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; THUMB2-NEXT: ldr r1, [r1]
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; THUMB2-NEXT: eors r0, r1
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; THUMB2-NEXT: lsls r0, r0, #24
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; THUMB2-NEXT: mov.w r0, #0
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; THUMB2-NEXT: it eq
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; THUMB2-NEXT: moveq r0, #1
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; THUMB2-NEXT: bx lr
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i32* nocapture readonly %b) {
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entry:
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%0 = load i32, i32* %a, align 4
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%1 = load i32, i32* %b, align 4
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%xor = xor i32 %1, %0
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%and = and i32 %xor, 255
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a,
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; ARM-LABEL: cmp_xor16:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldr r0, [r0]
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; ARM-NEXT: movw r2, #65535
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; ARM-NEXT: ldr r1, [r1]
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; ARM-NEXT: eor r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, r2
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_xor16:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldr r0, [r0]
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; ARMEB-NEXT: movw r2, #65535
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; ARMEB-NEXT: ldr r1, [r1]
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; ARMEB-NEXT: eor r1, r1, r0
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; ARMEB-NEXT: mov r0, #0
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; ARMEB-NEXT: tst r1, r2
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; ARMEB-NEXT: movweq r0, #1
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; ARMEB-NEXT: bx lr
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;
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; THUMB1-LABEL: cmp_xor16:
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; THUMB1: @ BB#0: @ %entry
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; THUMB1-NEXT: ldr r0, [r0]
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; THUMB1-NEXT: ldr r2, [r1]
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; THUMB1-NEXT: eors r2, r0
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; THUMB1-NEXT: movs r0, #1
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; THUMB1-NEXT: movs r1, #0
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; THUMB1-NEXT: lsls r2, r2, #16
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; THUMB1-NEXT: beq .LBB3_2
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; THUMB1-NEXT: @ BB#1: @ %entry
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; THUMB1-NEXT: mov r0, r1
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; THUMB1-NEXT: .LBB3_2: @ %entry
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; THUMB1-NEXT: bx lr
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;
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; THUMB2-LABEL: cmp_xor16:
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; THUMB2: @ BB#0: @ %entry
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; THUMB2-NEXT: ldr r0, [r0]
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; THUMB2-NEXT: ldr r1, [r1]
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; THUMB2-NEXT: eors r0, r1
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; THUMB2-NEXT: lsls r0, r0, #16
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; THUMB2-NEXT: mov.w r0, #0
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; THUMB2-NEXT: it eq
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; THUMB2-NEXT: moveq r0, #1
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; THUMB2-NEXT: bx lr
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i32* nocapture readonly %b) {
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entry:
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%0 = load i32, i32* %a, align 4
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%1 = load i32, i32* %b, align 4
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%xor = xor i32 %1, %0
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%and = and i32 %xor, 65535
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a,
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; ARM-LABEL: cmp_or8_short_short:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldrh r0, [r0]
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; ARM-NEXT: ldrh r1, [r1]
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; ARM-NEXT: orr r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, #255
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_or8_short_short:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldrh r0, [r0]
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; ARMEB-NEXT: ldrh r1, [r1]
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; ARMEB-NEXT: orr r1, r1, r0
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; ARMEB-NEXT: mov r0, #0
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; ARMEB-NEXT: tst r1, #255
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; ARMEB-NEXT: movweq r0, #1
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; ARMEB-NEXT: bx lr
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;
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; THUMB1-LABEL: cmp_or8_short_short:
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; THUMB1: @ BB#0: @ %entry
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; THUMB1-NEXT: ldrh r0, [r0]
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; THUMB1-NEXT: ldrh r2, [r1]
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; THUMB1-NEXT: orrs r2, r0
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; THUMB1-NEXT: movs r0, #1
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; THUMB1-NEXT: movs r1, #0
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; THUMB1-NEXT: lsls r2, r2, #24
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; THUMB1-NEXT: beq .LBB4_2
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; THUMB1-NEXT: @ BB#1: @ %entry
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; THUMB1-NEXT: mov r0, r1
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; THUMB1-NEXT: .LBB4_2: @ %entry
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; THUMB1-NEXT: bx lr
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;
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; THUMB2-LABEL: cmp_or8_short_short:
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; THUMB2: @ BB#0: @ %entry
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; THUMB2-NEXT: ldrh r0, [r0]
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; THUMB2-NEXT: ldrh r1, [r1]
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; THUMB2-NEXT: orrs r0, r1
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; THUMB2-NEXT: lsls r0, r0, #24
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; THUMB2-NEXT: mov.w r0, #0
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; THUMB2-NEXT: it eq
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; THUMB2-NEXT: moveq r0, #1
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; THUMB2-NEXT: bx lr
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i16* nocapture readonly %b) {
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entry:
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%0 = load i16, i16* %a, align 2
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%1 = load i16, i16* %b, align 2
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%or2 = or i16 %1, %0
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%2 = and i16 %or2, 255
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%cmp = icmp eq i16 %2, 0
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ret i1 %cmp
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}
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define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a,
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; ARM-LABEL: cmp_or8_short_int:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldrh r0, [r0]
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; ARM-NEXT: ldr r1, [r1]
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; ARM-NEXT: orr r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, #255
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_or8_short_int:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldrh r0, [r0]
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; ARMEB-NEXT: ldr r1, [r1]
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; ARMEB-NEXT: orr r1, r1, r0
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; ARMEB-NEXT: mov r0, #0
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; ARMEB-NEXT: tst r1, #255
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; ARMEB-NEXT: movweq r0, #1
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; ARMEB-NEXT: bx lr
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;
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; THUMB1-LABEL: cmp_or8_short_int:
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; THUMB1: @ BB#0: @ %entry
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; THUMB1-NEXT: ldrh r0, [r0]
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; THUMB1-NEXT: ldr r2, [r1]
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; THUMB1-NEXT: orrs r2, r0
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; THUMB1-NEXT: movs r0, #1
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; THUMB1-NEXT: movs r1, #0
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; THUMB1-NEXT: lsls r2, r2, #24
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; THUMB1-NEXT: beq .LBB5_2
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; THUMB1-NEXT: @ BB#1: @ %entry
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; THUMB1-NEXT: mov r0, r1
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; THUMB1-NEXT: .LBB5_2: @ %entry
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; THUMB1-NEXT: bx lr
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;
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; THUMB2-LABEL: cmp_or8_short_int:
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; THUMB2: @ BB#0: @ %entry
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; THUMB2-NEXT: ldrh r0, [r0]
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; THUMB2-NEXT: ldr r1, [r1]
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; THUMB2-NEXT: orrs r0, r1
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; THUMB2-NEXT: lsls r0, r0, #24
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; THUMB2-NEXT: mov.w r0, #0
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; THUMB2-NEXT: it eq
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; THUMB2-NEXT: moveq r0, #1
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; THUMB2-NEXT: bx lr
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i32* nocapture readonly %b) {
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entry:
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%0 = load i16, i16* %a, align 2
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%conv = zext i16 %0 to i32
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%1 = load i32, i32* %b, align 4
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%or = or i32 %1, %conv
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%and = and i32 %or, 255
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a,
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; ARM-LABEL: cmp_or8_int_int:
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; ARM: @ BB#0: @ %entry
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; ARM-NEXT: ldr r0, [r0]
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; ARM-NEXT: ldr r1, [r1]
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; ARM-NEXT: orr r1, r1, r0
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; ARM-NEXT: mov r0, #0
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; ARM-NEXT: tst r1, #255
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; ARM-NEXT: movweq r0, #1
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; ARM-NEXT: bx lr
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;
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; ARMEB-LABEL: cmp_or8_int_int:
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; ARMEB: @ BB#0: @ %entry
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; ARMEB-NEXT: ldr r0, [r0]
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; ARMEB-NEXT: ldr r1, [r1]
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; ARMEB-NEXT: orr r1, r1, r0
|
||||
; ARMEB-NEXT: mov r0, #0
|
||||
; ARMEB-NEXT: tst r1, #255
|
||||
; ARMEB-NEXT: movweq r0, #1
|
||||
; ARMEB-NEXT: bx lr
|
||||
;
|
||||
; THUMB1-LABEL: cmp_or8_int_int:
|
||||
; THUMB1: @ BB#0: @ %entry
|
||||
; THUMB1-NEXT: ldr r0, [r0]
|
||||
; THUMB1-NEXT: ldr r2, [r1]
|
||||
; THUMB1-NEXT: orrs r2, r0
|
||||
; THUMB1-NEXT: movs r0, #1
|
||||
; THUMB1-NEXT: movs r1, #0
|
||||
; THUMB1-NEXT: lsls r2, r2, #24
|
||||
; THUMB1-NEXT: beq .LBB6_2
|
||||
; THUMB1-NEXT: @ BB#1: @ %entry
|
||||
; THUMB1-NEXT: mov r0, r1
|
||||
; THUMB1-NEXT: .LBB6_2: @ %entry
|
||||
; THUMB1-NEXT: bx lr
|
||||
;
|
||||
; THUMB2-LABEL: cmp_or8_int_int:
|
||||
; THUMB2: @ BB#0: @ %entry
|
||||
; THUMB2-NEXT: ldr r0, [r0]
|
||||
; THUMB2-NEXT: ldr r1, [r1]
|
||||
; THUMB2-NEXT: orrs r0, r1
|
||||
; THUMB2-NEXT: lsls r0, r0, #24
|
||||
; THUMB2-NEXT: mov.w r0, #0
|
||||
; THUMB2-NEXT: it eq
|
||||
; THUMB2-NEXT: moveq r0, #1
|
||||
; THUMB2-NEXT: bx lr
|
||||
i32* nocapture readonly %b) {
|
||||
entry:
|
||||
%0 = load i32, i32* %a, align 4
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%or = or i32 %1, %0
|
||||
%and = and i32 %or, 255
|
||||
%cmp = icmp eq i32 %and, 0
|
||||
ret i1 %cmp
|
||||
}
|
||||
|
||||
define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a,
|
||||
; ARM-LABEL: cmp_or16:
|
||||
; ARM: @ BB#0: @ %entry
|
||||
; ARM-NEXT: ldr r0, [r0]
|
||||
; ARM-NEXT: movw r2, #65535
|
||||
; ARM-NEXT: ldr r1, [r1]
|
||||
; ARM-NEXT: orr r1, r1, r0
|
||||
; ARM-NEXT: mov r0, #0
|
||||
; ARM-NEXT: tst r1, r2
|
||||
; ARM-NEXT: movweq r0, #1
|
||||
; ARM-NEXT: bx lr
|
||||
;
|
||||
; ARMEB-LABEL: cmp_or16:
|
||||
; ARMEB: @ BB#0: @ %entry
|
||||
; ARMEB-NEXT: ldr r0, [r0]
|
||||
; ARMEB-NEXT: movw r2, #65535
|
||||
; ARMEB-NEXT: ldr r1, [r1]
|
||||
; ARMEB-NEXT: orr r1, r1, r0
|
||||
; ARMEB-NEXT: mov r0, #0
|
||||
; ARMEB-NEXT: tst r1, r2
|
||||
; ARMEB-NEXT: movweq r0, #1
|
||||
; ARMEB-NEXT: bx lr
|
||||
;
|
||||
; THUMB1-LABEL: cmp_or16:
|
||||
; THUMB1: @ BB#0: @ %entry
|
||||
; THUMB1-NEXT: ldr r0, [r0]
|
||||
; THUMB1-NEXT: ldr r2, [r1]
|
||||
; THUMB1-NEXT: orrs r2, r0
|
||||
; THUMB1-NEXT: movs r0, #1
|
||||
; THUMB1-NEXT: movs r1, #0
|
||||
; THUMB1-NEXT: lsls r2, r2, #16
|
||||
; THUMB1-NEXT: beq .LBB7_2
|
||||
; THUMB1-NEXT: @ BB#1: @ %entry
|
||||
; THUMB1-NEXT: mov r0, r1
|
||||
; THUMB1-NEXT: .LBB7_2: @ %entry
|
||||
; THUMB1-NEXT: bx lr
|
||||
;
|
||||
; THUMB2-LABEL: cmp_or16:
|
||||
; THUMB2: @ BB#0: @ %entry
|
||||
; THUMB2-NEXT: ldr r0, [r0]
|
||||
; THUMB2-NEXT: ldr r1, [r1]
|
||||
; THUMB2-NEXT: orrs r0, r1
|
||||
; THUMB2-NEXT: lsls r0, r0, #16
|
||||
; THUMB2-NEXT: mov.w r0, #0
|
||||
; THUMB2-NEXT: it eq
|
||||
; THUMB2-NEXT: moveq r0, #1
|
||||
; THUMB2-NEXT: bx lr
|
||||
i32* nocapture readonly %b) {
|
||||
entry:
|
||||
%0 = load i32, i32* %a, align 4
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%or = or i32 %1, %0
|
||||
%and = and i32 %or, 65535
|
||||
%cmp = icmp eq i32 %and, 0
|
||||
ret i1 %cmp
|
||||
}
|
||||
|
||||
define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
|
||||
; ARM-LABEL: cmp_and8_short_short:
|
||||
; ARM: @ BB#0: @ %entry
|
||||
; ARM-NEXT: ldrh r1, [r1]
|
||||
; ARM-NEXT: ldrh r0, [r0]
|
||||
; ARM-NEXT: and r1, r0, r1
|
||||
; ARM-NEXT: mov r0, #0
|
||||
; ARM-NEXT: tst r1, #255
|
||||
; ARM-NEXT: movweq r0, #1
|
||||
; ARM-NEXT: bx lr
|
||||
;
|
||||
; ARMEB-LABEL: cmp_and8_short_short:
|
||||
; ARMEB: @ BB#0: @ %entry
|
||||
; ARMEB-NEXT: ldrh r1, [r1]
|
||||
; ARMEB-NEXT: ldrh r0, [r0]
|
||||
; ARMEB-NEXT: and r1, r0, r1
|
||||
; ARMEB-NEXT: mov r0, #0
|
||||
; ARMEB-NEXT: tst r1, #255
|
||||
; ARMEB-NEXT: movweq r0, #1
|
||||
; ARMEB-NEXT: bx lr
|
||||
;
|
||||
; THUMB1-LABEL: cmp_and8_short_short:
|
||||
; THUMB1: @ BB#0: @ %entry
|
||||
; THUMB1-NEXT: ldrh r1, [r1]
|
||||
; THUMB1-NEXT: ldrh r2, [r0]
|
||||
; THUMB1-NEXT: ands r2, r1
|
||||
; THUMB1-NEXT: movs r0, #1
|
||||
; THUMB1-NEXT: movs r1, #0
|
||||
; THUMB1-NEXT: lsls r2, r2, #24
|
||||
; THUMB1-NEXT: beq .LBB8_2
|
||||
; THUMB1-NEXT: @ BB#1: @ %entry
|
||||
; THUMB1-NEXT: mov r0, r1
|
||||
; THUMB1-NEXT: .LBB8_2: @ %entry
|
||||
; THUMB1-NEXT: bx lr
|
||||
;
|
||||
; THUMB2-LABEL: cmp_and8_short_short:
|
||||
; THUMB2: @ BB#0: @ %entry
|
||||
; THUMB2-NEXT: ldrh r1, [r1]
|
||||
; THUMB2-NEXT: ldrh r0, [r0]
|
||||
; THUMB2-NEXT: ands r0, r1
|
||||
; THUMB2-NEXT: lsls r0, r0, #24
|
||||
; THUMB2-NEXT: mov.w r0, #0
|
||||
; THUMB2-NEXT: it eq
|
||||
; THUMB2-NEXT: moveq r0, #1
|
||||
; THUMB2-NEXT: bx lr
|
||||
i16* nocapture readonly %b) {
|
||||
entry:
|
||||
%0 = load i16, i16* %a, align 2
|
||||
%1 = load i16, i16* %b, align 2
|
||||
%and3 = and i16 %0, 255
|
||||
%2 = and i16 %and3, %1
|
||||
%cmp = icmp eq i16 %2, 0
|
||||
ret i1 %cmp
|
||||
}
|
||||
|
||||
define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a,
|
||||
; ARM-LABEL: cmp_and8_short_int:
|
||||
; ARM: @ BB#0: @ %entry
|
||||
; ARM-NEXT: ldrh r0, [r0]
|
||||
; ARM-NEXT: ldr r1, [r1]
|
||||
; ARM-NEXT: and r1, r1, r0
|
||||
; ARM-NEXT: mov r0, #0
|
||||
; ARM-NEXT: tst r1, #255
|
||||
; ARM-NEXT: movweq r0, #1
|
||||
; ARM-NEXT: bx lr
|
||||
;
|
||||
; ARMEB-LABEL: cmp_and8_short_int:
|
||||
; ARMEB: @ BB#0: @ %entry
|
||||
; ARMEB-NEXT: ldrh r0, [r0]
|
||||
; ARMEB-NEXT: ldr r1, [r1]
|
||||
; ARMEB-NEXT: and r1, r1, r0
|
||||
; ARMEB-NEXT: mov r0, #0
|
||||
; ARMEB-NEXT: tst r1, #255
|
||||
; ARMEB-NEXT: movweq r0, #1
|
||||
; ARMEB-NEXT: bx lr
|
||||
;
|
||||
; THUMB1-LABEL: cmp_and8_short_int:
|
||||
; THUMB1: @ BB#0: @ %entry
|
||||
; THUMB1-NEXT: ldrh r0, [r0]
|
||||
; THUMB1-NEXT: ldr r2, [r1]
|
||||
; THUMB1-NEXT: ands r2, r0
|
||||
; THUMB1-NEXT: movs r0, #1
|
||||
; THUMB1-NEXT: movs r1, #0
|
||||
; THUMB1-NEXT: lsls r2, r2, #24
|
||||
; THUMB1-NEXT: beq .LBB9_2
|
||||
; THUMB1-NEXT: @ BB#1: @ %entry
|
||||
; THUMB1-NEXT: mov r0, r1
|
||||
; THUMB1-NEXT: .LBB9_2: @ %entry
|
||||
; THUMB1-NEXT: bx lr
|
||||
;
|
||||
; THUMB2-LABEL: cmp_and8_short_int:
|
||||
; THUMB2: @ BB#0: @ %entry
|
||||
; THUMB2-NEXT: ldrh r0, [r0]
|
||||
; THUMB2-NEXT: ldr r1, [r1]
|
||||
; THUMB2-NEXT: ands r0, r1
|
||||
; THUMB2-NEXT: lsls r0, r0, #24
|
||||
; THUMB2-NEXT: mov.w r0, #0
|
||||
; THUMB2-NEXT: it eq
|
||||
; THUMB2-NEXT: moveq r0, #1
|
||||
; THUMB2-NEXT: bx lr
|
||||
i32* nocapture readonly %b) {
|
||||
entry:
|
||||
%0 = load i16, i16* %a, align 2
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%2 = and i16 %0, 255
|
||||
%and = zext i16 %2 to i32
|
||||
%and1 = and i32 %1, %and
|
||||
%cmp = icmp eq i32 %and1, 0
|
||||
ret i1 %cmp
|
||||
}
|
||||
|
||||
define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a,
|
||||
; ARM-LABEL: cmp_and8_int_int:
|
||||
; ARM: @ BB#0: @ %entry
|
||||
; ARM-NEXT: ldr r1, [r1]
|
||||
; ARM-NEXT: ldr r0, [r0]
|
||||
; ARM-NEXT: and r1, r0, r1
|
||||
; ARM-NEXT: mov r0, #0
|
||||
; ARM-NEXT: tst r1, #255
|
||||
; ARM-NEXT: movweq r0, #1
|
||||
; ARM-NEXT: bx lr
|
||||
;
|
||||
; ARMEB-LABEL: cmp_and8_int_int:
|
||||
; ARMEB: @ BB#0: @ %entry
|
||||
; ARMEB-NEXT: ldr r1, [r1]
|
||||
; ARMEB-NEXT: ldr r0, [r0]
|
||||
; ARMEB-NEXT: and r1, r0, r1
|
||||
; ARMEB-NEXT: mov r0, #0
|
||||
; ARMEB-NEXT: tst r1, #255
|
||||
; ARMEB-NEXT: movweq r0, #1
|
||||
; ARMEB-NEXT: bx lr
|
||||
;
|
||||
; THUMB1-LABEL: cmp_and8_int_int:
|
||||
; THUMB1: @ BB#0: @ %entry
|
||||
; THUMB1-NEXT: ldr r1, [r1]
|
||||
; THUMB1-NEXT: ldr r2, [r0]
|
||||
; THUMB1-NEXT: ands r2, r1
|
||||
; THUMB1-NEXT: movs r0, #1
|
||||
; THUMB1-NEXT: movs r1, #0
|
||||
; THUMB1-NEXT: lsls r2, r2, #24
|
||||
; THUMB1-NEXT: beq .LBB10_2
|
||||
; THUMB1-NEXT: @ BB#1: @ %entry
|
||||
; THUMB1-NEXT: mov r0, r1
|
||||
; THUMB1-NEXT: .LBB10_2: @ %entry
|
||||
; THUMB1-NEXT: bx lr
|
||||
;
|
||||
; THUMB2-LABEL: cmp_and8_int_int:
|
||||
; THUMB2: @ BB#0: @ %entry
|
||||
; THUMB2-NEXT: ldr r1, [r1]
|
||||
; THUMB2-NEXT: ldr r0, [r0]
|
||||
; THUMB2-NEXT: ands r0, r1
|
||||
; THUMB2-NEXT: lsls r0, r0, #24
|
||||
; THUMB2-NEXT: mov.w r0, #0
|
||||
; THUMB2-NEXT: it eq
|
||||
; THUMB2-NEXT: moveq r0, #1
|
||||
; THUMB2-NEXT: bx lr
|
||||
i32* nocapture readonly %b) {
|
||||
entry:
|
||||
%0 = load i32, i32* %a, align 4
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%and = and i32 %0, 255
|
||||
%and1 = and i32 %and, %1
|
||||
%cmp = icmp eq i32 %and1, 0
|
||||
ret i1 %cmp
|
||||
}
|
||||
|
||||
define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a,
|
||||
; ARM-LABEL: cmp_and16:
|
||||
; ARM: @ BB#0: @ %entry
|
||||
; ARM-NEXT: ldr r1, [r1]
|
||||
; ARM-NEXT: movw r2, #65535
|
||||
; ARM-NEXT: ldr r0, [r0]
|
||||
; ARM-NEXT: and r1, r0, r1
|
||||
; ARM-NEXT: mov r0, #0
|
||||
; ARM-NEXT: tst r1, r2
|
||||
; ARM-NEXT: movweq r0, #1
|
||||
; ARM-NEXT: bx lr
|
||||
;
|
||||
; ARMEB-LABEL: cmp_and16:
|
||||
; ARMEB: @ BB#0: @ %entry
|
||||
; ARMEB-NEXT: ldr r1, [r1]
|
||||
; ARMEB-NEXT: movw r2, #65535
|
||||
; ARMEB-NEXT: ldr r0, [r0]
|
||||
; ARMEB-NEXT: and r1, r0, r1
|
||||
; ARMEB-NEXT: mov r0, #0
|
||||
; ARMEB-NEXT: tst r1, r2
|
||||
; ARMEB-NEXT: movweq r0, #1
|
||||
; ARMEB-NEXT: bx lr
|
||||
;
|
||||
; THUMB1-LABEL: cmp_and16:
|
||||
; THUMB1: @ BB#0: @ %entry
|
||||
; THUMB1-NEXT: ldr r1, [r1]
|
||||
; THUMB1-NEXT: ldr r2, [r0]
|
||||
; THUMB1-NEXT: ands r2, r1
|
||||
; THUMB1-NEXT: movs r0, #1
|
||||
; THUMB1-NEXT: movs r1, #0
|
||||
; THUMB1-NEXT: lsls r2, r2, #16
|
||||
; THUMB1-NEXT: beq .LBB11_2
|
||||
; THUMB1-NEXT: @ BB#1: @ %entry
|
||||
; THUMB1-NEXT: mov r0, r1
|
||||
; THUMB1-NEXT: .LBB11_2: @ %entry
|
||||
; THUMB1-NEXT: bx lr
|
||||
;
|
||||
; THUMB2-LABEL: cmp_and16:
|
||||
; THUMB2: @ BB#0: @ %entry
|
||||
; THUMB2-NEXT: ldr r1, [r1]
|
||||
; THUMB2-NEXT: ldr r0, [r0]
|
||||
; THUMB2-NEXT: ands r0, r1
|
||||
; THUMB2-NEXT: lsls r0, r0, #16
|
||||
; THUMB2-NEXT: mov.w r0, #0
|
||||
; THUMB2-NEXT: it eq
|
||||
; THUMB2-NEXT: moveq r0, #1
|
||||
; THUMB2-NEXT: bx lr
|
||||
i32* nocapture readonly %b) {
|
||||
entry:
|
||||
%0 = load i32, i32* %a, align 4
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%and = and i32 %0, 65535
|
||||
%and1 = and i32 %and, %1
|
||||
%cmp = icmp eq i32 %and1, 0
|
||||
ret i1 %cmp
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user