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[X86][NFC] Pre-commit test to show prolog insert problem
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llvm/test/CodeGen/X86/vaargs-prolog-insert.ll
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45
llvm/test/CodeGen/X86/vaargs-prolog-insert.ll
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@ -0,0 +1,45 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
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; Check the prolog won't be sunk across the save of CSRs.
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define void @reduce(i32, i32, i32, i32, i32, i32, ...) nounwind {
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; CHECK-LABEL: reduce:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB0_4
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps %xmm4, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps %xmm5, (%rsp)
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; CHECK-NEXT: movaps %xmm6, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movaps %xmm7, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: subq $56, %rsp
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; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq %rax, 16
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; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq %rax, 8
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; CHECK-NEXT: movl $48, 4
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; CHECK-NEXT: movl $48, 0
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; CHECK-NEXT: addq $56, %rsp
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: retq
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br i1 undef, label %8, label %7
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7: ; preds = %6
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call void @llvm.va_start(i8* null)
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br label %8
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8: ; preds = %7, %6
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ret void
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}
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_end(i8*)
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