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[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

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For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.

Test added here:

  CodeGen/AArch64/vselect-constants.ll

Differential Revision: https://reviews.llvm.org/D113994
This commit is contained in:
David Sherwood 2021-11-16 14:19:18 +00:00
parent 35f798d05d
commit 4607459022
2 changed files with 21 additions and 1 deletions
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4
llvm/lib/Target/AArch64/AArch64ISelLowering.h
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@ -743,7 +743,9 @@ public:
if (!VT.isVector())
return hasAndNotCompare(Y);
return VT.getSizeInBits() >= 64; // vector 'bic'
TypeSize TS = VT.getSizeInBits();
// TODO: We should be able to use bic/bif too for SVE.
return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
}
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(

18
llvm/test/CodeGen/AArch64/vselect-constants.ll
View File

@ -363,3 +363,21 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
%r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
ret <2 x i64> %r
}
; SVE
define <vscale x 16 x i8> @signbit_mask_xor_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: signbit_mask_xor_nxv16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: cmplt p0.b, p0/z, z0.b, #0
; CHECK-NEXT: eor z0.d, z0.d, z1.d
; CHECK-NEXT: mov z0.b, p0/m, #0 // =0x0
; CHECK-NEXT: ret
%cond = icmp slt <vscale x 16 x i8> %a, zeroinitializer
%xor = xor <vscale x 16 x i8> %a, %b
%r = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %xor
ret <vscale x 16 x i8> %r
}
attributes #0 = { "target-features"="+sve" }