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Revert "[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points."

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This reverts commit 5ec1353523.
This commit is contained in:
Konstantina Mitropoulou 2023-08-24 19:20:27 -07:00
parent 653f77690b
commit 48fa79a503
5 changed files with 1547 additions and 2016 deletions
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6
llvm/include/llvm/CodeGen/ISDOpcodes.h
View File

@ -1543,12 +1543,6 @@ inline bool isIntEqualitySetCC(CondCode Code) {
return Code == SETEQ || Code == SETNE;
}
/// Return true if this is a setcc instruction that performs an equality
/// comparison when used with floating point operands.
inline bool isFPEqualitySetCC(CondCode Code) {
return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE;
}
/// Return true if the specified condition returns true if the two operands to
/// the condition are equal. Note that if one of the two operands is a NaN,
/// this value is meaningless.

109
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6042,67 +6042,6 @@ SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
return SDValue();
}
static bool arebothOperandsNotSNan(SDValue Operand1, SDValue Operand2,
SelectionDAG &DAG) {
return DAG.isKnownNeverSNaN(Operand2) && DAG.isKnownNeverSNaN(Operand1);
}
static bool arebothOperandsNotNan(SDValue Operand1, SDValue Operand2,
SelectionDAG &DAG) {
return DAG.isKnownNeverNaN(Operand2) && DAG.isKnownNeverNaN(Operand1);
}
static unsigned getMinMaxOpcodeForFP(SDValue Operand1, SDValue Operand2,
ISD::CondCode CC, unsigned OrAndOpcode,
SelectionDAG &DAG) {
// The optimization cannot be applied for all the predicates because
// of the way FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle
// NaNs. For FMINNUM_IEEE/FMAXNUM_IEEE, the optimization cannot be
// applied at all if one of the operands is a signaling NaN.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
EVT OpVT = Operand1.getValueType();
// It is safe to use FMINNUM_IEEE/FMAXNUM_IEEE if all the operands
// are non NaN values.
if (((CC == ISD::SETLT || CC == ISD::SETLE) && (OrAndOpcode == ISD::OR)) ||
((CC == ISD::SETGT || CC == ISD::SETGE) && (OrAndOpcode == ISD::AND)))
return arebothOperandsNotNan(Operand1, Operand2, DAG) ? ISD::FMINNUM_IEEE
: ISD::DELETED_NODE;
else if (((CC == ISD::SETGT || CC == ISD::SETGE) &&
(OrAndOpcode == ISD::OR)) ||
((CC == ISD::SETLT || CC == ISD::SETLE) &&
(OrAndOpcode == ISD::AND)))
return arebothOperandsNotNan(Operand1, Operand2, DAG) ? ISD::FMAXNUM_IEEE
: ISD::DELETED_NODE;
// Both FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle quiet
// NaNs in the same way. But, FMINNUM/FMAXNUM and FMINNUM_IEEE/
// FMAXNUM_IEEE handle signaling NaNs differently. If we cannot prove
// that there are not any sNaNs, then the optimization is not valid
// for FMINNUM_IEEE/FMAXNUM_IEEE. In the presence of sNaNs, we apply
// the optimization using FMINNUM/FMAXNUM for the following cases. If
// we can prove that we do not have any sNaNs, then we can do the
// optimization using FMINNUM_IEEE/FMAXNUM_IEEE for the following
// cases.
else if (((CC == ISD::SETOLT || CC == ISD::SETOLE) &&
(OrAndOpcode == ISD::OR)) ||
((CC == ISD::SETUGT || CC == ISD::SETUGE) &&
(OrAndOpcode == ISD::AND)))
return TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT)
? ISD::FMINNUM
: arebothOperandsNotSNan(Operand1, Operand2, DAG)
? ISD::FMINNUM_IEEE
: ISD::DELETED_NODE;
else if (((CC == ISD::SETOGT || CC == ISD::SETOGE) &&
(OrAndOpcode == ISD::OR)) ||
((CC == ISD::SETULT || CC == ISD::SETULE) &&
(OrAndOpcode == ISD::AND)))
return TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT)
? ISD::FMAXNUM
: arebothOperandsNotSNan(Operand1, Operand2, DAG)
? ISD::FMAXNUM_IEEE
: ISD::DELETED_NODE;
return ISD::DELETED_NODE;
}
static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
using AndOrSETCCFoldKind = TargetLowering::AndOrSETCCFoldKind;
assert(
@ -6144,20 +6083,12 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
// The optimization does not work for `==` or `!=` .
// The two comparisons should have either the same predicate or the
// predicate of one of the comparisons is the opposite of the other one.
if (((OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
TLI.isOperationLegal(ISD::SMAX, OpVT) &&
TLI.isOperationLegal(ISD::UMIN, OpVT) &&
TLI.isOperationLegal(ISD::SMIN, OpVT)) ||
(OpVT.isFloatingPoint() &&
((TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT) &&
TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT)) ||
(TLI.isOperationLegal(ISD::FMAXNUM_IEEE, OpVT) &&
TLI.isOperationLegal(ISD::FMINNUM_IEEE, OpVT))))) &&
!ISD::isIntEqualitySetCC(CCL) && !ISD::isFPEqualitySetCC(CCL) &&
CCL != ISD::SETFALSE && CCL != ISD::SETO && CCL != ISD::SETUO &&
CCL != ISD::SETTRUE &&
(CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR))) {
if (OpVT.isInteger() && !ISD::isIntEqualitySetCC(CCL) &&
(CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
TLI.isOperationLegal(ISD::UMAX, OpVT) &&
TLI.isOperationLegal(ISD::SMAX, OpVT) &&
TLI.isOperationLegal(ISD::UMIN, OpVT) &&
TLI.isOperationLegal(ISD::SMIN, OpVT)) {
SDValue CommonValue, Operand1, Operand2;
ISD::CondCode CC = ISD::SETCC_INVALID;
if (CCL == CCR) {
@ -6195,25 +6126,19 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
CC = ISD::SETCC_INVALID;
if (CC != ISD::SETCC_INVALID) {
unsigned NewOpcode = ISD::DELETED_NODE;
unsigned NewOpcode;
bool IsSigned = isSignedIntSetCC(CC);
if (OpVT.isInteger()) {
bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE ||
CC == ISD::SETLT || CC == ISD::SETULT);
bool IsOr = (LogicOp->getOpcode() == ISD::OR);
if (IsLess == IsOr)
NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
else
NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
} else if (OpVT.isFloatingPoint())
NewOpcode = getMinMaxOpcodeForFP(Operand1, Operand2, CC,
LogicOp->getOpcode(), DAG);
bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE ||
CC == ISD::SETLT || CC == ISD::SETULT);
bool IsOr = (LogicOp->getOpcode() == ISD::OR);
if (IsLess == IsOr)
NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
else
NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
if (NewOpcode != ISD::DELETED_NODE) {
SDValue MinMaxValue =
DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
}
SDValue MinMaxValue =
DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
}
}

3296
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
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File diff suppressed because it is too large Load Diff

65
llvm/test/CodeGen/AMDGPU/fma.f16.ll
View File

@ -92,30 +92,18 @@ define half @test_fmamk(half %x, half %y, half %z) {
; Regression test for a crash caused by D139469.
define i32 @test_D139469_f16(half %arg) {
; GFX9-SDAG-LABEL: test_D139469_f16:
; GFX9-SDAG: ; %bb.0: ; %bb
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_D139469_f16:
; GFX9-GISEL: ; %bb.0: ; %bb
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_mul_f16_e32 v1, 0x291e, v0
; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x291e
; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e
; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, s4, v1
; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: test_D139469_f16:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_f16_e32 v1, 0x291e, v0
; GFX9-NEXT: s_movk_i32 s4, 0x291e
; GFX9-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0x211e
; GFX9-NEXT: v_fma_f16 v0, v0, s4, v1
; GFX9-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_D139469_f16:
; GFX10-SDAG: ; %bb.0: ; %bb
@ -123,9 +111,10 @@ define i32 @test_D139469_f16(half %arg) {
; GFX10-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
; GFX10-SDAG-NEXT: v_mul_f16_e32 v2, 0x291e, v0
; GFX10-SDAG-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
; GFX10-SDAG-NEXT: v_min_f16_e32 v0, v2, v1
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e64 s4, 0, v1
; GFX10-SDAG-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_D139469_f16:
@ -154,14 +143,17 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX9-SDAG: ; %bb.0: ; %bb
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
; GFX9-SDAG-NEXT: v_pk_mul_f16 v1, v0, s4 op_sel_hi:[1,0]
; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v0, s4, v2 op_sel_hi:[1,0,0]
; GFX9-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v0, s4, v1 op_sel_hi:[1,0,0]
; GFX9-SDAG-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[8:9], v0, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX9-SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-SDAG-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@ -190,10 +182,13 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX10-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
; GFX10-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s4 op_sel_hi:[0,1,0]
; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e64 s4, 0, v0
; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s5, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s6, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
; GFX10-SDAG-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-SDAG-NEXT: s_or_b32 s4, s5, s6
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;

87
llvm/test/CodeGen/AMDGPU/or.ll
View File

@ -1160,74 +1160,77 @@ define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, p
; GFX6-LABEL: or_i1:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s10, s2
; GFX6-NEXT: s_mov_b32 s11, s3
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_mov_b32 s2, s10
; GFX6-NEXT: s_mov_b32 s3, s11
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s12, s6
; GFX6-NEXT: s_mov_b32 s13, s7
; GFX6-NEXT: s_mov_b32 s14, s2
; GFX6-NEXT: s_mov_b32 s15, s3
; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
; GFX6-NEXT: s_mov_b32 s14, s10
; GFX6-NEXT: s_mov_b32 s15, s11
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GFX6-NEXT: buffer_load_dword v1, off, s[12:15], 0
; GFX6-NEXT: s_mov_b32 s0, s4
; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: s_mov_b32 s8, s4
; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: s_waitcnt vmcnt(1)
; GFX6-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v1
; GFX6-NEXT: v_max_f32_e32 v0, v1, v0
; GFX6-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: or_i1:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1
; GFX8-NEXT: s_mov_b32 s10, s2
; GFX8-NEXT: s_mov_b32 s11, s3
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX8-NEXT: s_mov_b32 s11, 0xf000
; GFX8-NEXT: s_mov_b32 s10, -1
; GFX8-NEXT: s_mov_b32 s2, s10
; GFX8-NEXT: s_mov_b32 s3, s11
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_mov_b32 s13, s7
; GFX8-NEXT: s_mov_b32 s14, s2
; GFX8-NEXT: s_mov_b32 s15, s3
; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
; GFX8-NEXT: s_mov_b32 s14, s10
; GFX8-NEXT: s_mov_b32 s15, s11
; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GFX8-NEXT: buffer_load_dword v1, off, s[12:15], 0
; GFX8-NEXT: s_mov_b32 s0, s4
; GFX8-NEXT: s_mov_b32 s1, s5
; GFX8-NEXT: s_mov_b32 s8, s4
; GFX8-NEXT: s_mov_b32 s9, s5
; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mul_f32_e32 v1, 1.0, v1
; GFX8-NEXT: v_max_f32_e32 v0, v1, v0
; GFX8-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX8-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: or_i1:
; EG: ; %bb.0:
; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6
; EG-NEXT: ALU 4, @12, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @8
; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @10
; EG-NEXT: ALU 5, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1
; EG-NEXT: Fetch clause starting at 8:
; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV T0.X, KC0[2].Z,
; EG-NEXT: MOV * T1.X, KC0[2].W,
; EG-NEXT: Fetch clause starting at 10:
; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1
; EG-NEXT: ALU clause starting at 12:
; EG-NEXT: MAX_DX10 * T0.W, T0.X, T1.X,
; EG-NEXT: SETGE_DX10 * T0.W, PV.W, 0.0,
; EG-NEXT: MOV * T0.X, KC0[2].W,
; EG-NEXT: ALU clause starting at 13:
; EG-NEXT: MOV * T1.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 14:
; EG-NEXT: SETGE_DX10 T0.W, T0.X, 0.0,
; EG-NEXT: SETGE_DX10 * T1.W, T1.X, 0.0,
; EG-NEXT: OR_INT * T0.W, PS, PV.W,
; EG-NEXT: AND_INT T0.X, PV.W, 1,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)