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[x86] Introduce the enclv instruction

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Summary:
and use the -msgx flag as a requirement
for the SGX instructions.

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D46436

llvm-svn: 331742
This commit is contained in:
Gabor Buella 2018-05-08 07:11:05 +00:00
parent 51cebc98f3
commit 4a02bf945e
10 changed files with 49 additions and 30 deletions
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1
llvm/lib/Target/X86/X86InstrInfo.td
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@ -881,6 +881,7 @@ def HasIFMA : Predicate<"Subtarget->hasIFMA()">;
def HasRTM : Predicate<"Subtarget->hasRTM()">;
def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">;
def HasSGX : Predicate<"Subtarget->hasSGX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;

6
llvm/lib/Target/X86/X86InstrSGX.td
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@ -15,7 +15,7 @@
//===----------------------------------------------------------------------===//
// SGX instructions
let SchedRW = [WriteSystem] in {
let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
// ENCLS - Execute an Enclave System Function of Specified Leaf Number
def ENCLS : I<0x01, MRM_CF, (outs), (ins),
"encls", []>, TB;
@ -23,4 +23,8 @@ def ENCLS : I<0x01, MRM_CF, (outs), (ins),
// ENCLU - Execute an Enclave User Function of Specified Leaf Number
def ENCLU : I<0x01, MRM_D7, (outs), (ins),
"enclu", []>, TB;
// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number
def ENCLV : I<0x01, MRM_C0, (outs), (ins),
"enclv", []>, TB;
} // SchedRW

1
llvm/lib/Target/X86/X86Subtarget.h
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@ -644,6 +644,7 @@ public:
bool hasRDPID() const { return HasRDPID; }
bool hasWAITPKG() const { return HasWAITPKG; }
bool hasPCONFIG() const { return HasPCONFIG; }
bool hasSGX() const { return HasSGX; }
bool useRetpoline() const { return UseRetpoline; }
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }

9
llvm/test/MC/Disassembler/X86/x86-32.txt
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@ -874,3 +874,12 @@
#CHECK: pconfig
0x0f 0x01 0xc5
#CHECK: encls
0x0f 0x01 0xcf
#CHECK: enclu
0x0f 0x01 0xd7
#CHECK: enclv
0x0f 0x01 0xc0

9
llvm/test/MC/Disassembler/X86/x86-64.txt
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@ -567,3 +567,12 @@
#CHECK: pconfig
0x0f 0x01 0xc5
#CHECK: encls
0x0f 0x01 0xcf
#CHECK: enclu
0x0f 0x01 0xd7
#CHECK: enclv
0x0f 0x01 0xc0

10
llvm/test/MC/X86/SGX-32.s
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@ -1,10 +0,0 @@
// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

10
llvm/test/MC/X86/SGX-64.s
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@ -1,10 +0,0 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

9
llvm/test/MC/X86/sgx-encoding.s
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@ -1,9 +0,0 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

12
llvm/test/MC/X86/x86-32-coverage.s
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@ -10796,3 +10796,15 @@ btcl $4, (%eax)
// CHECK: pconfig
// CHECK: # encoding: [0x0f,0x01,0xc5]
pconfig
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu
// CHECK: enclv
// CHECK: encoding: [0x0f,0x01,0xc0]
enclv

12
llvm/test/MC/X86/x86-64.s
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@ -1623,6 +1623,18 @@ movdir64b (%rdx), %r15
// CHECK: # encoding: [0x0f,0x01,0xc5]
pconfig
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu
// CHECK: enclv
// CHECK: encoding: [0x0f,0x01,0xc0]
enclv
// __asm __volatile(
// "pushf \n\t"
// "popf \n\t"