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https://github.com/capstone-engine/llvm-capstone.git
synced 2025-04-01 12:43:47 +00:00
AMDGPU: Fix not converting d16 load/stores to offset
Fixes missed optimization with new MUBUF instructions. llvm-svn: 318106
This commit is contained in:
Matt Arsenault
parent
c8434103d0
commit
4b7938c658
@ -435,6 +435,10 @@ static int getOffsetMUBUFStore(unsigned Opc) {
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return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET;
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case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN:
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return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET;
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case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN:
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return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET;
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case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN:
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return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET;
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default:
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return -1;
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}
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@ -456,6 +460,18 @@ static int getOffsetMUBUFLoad(unsigned Opc) {
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return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET;
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case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN:
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return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET;
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case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN:
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return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET;
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case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN:
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return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET;
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case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN:
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return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET;
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case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN:
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return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET;
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case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN:
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return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET;
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case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN:
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return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET;
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default:
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return -1;
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}
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@ -479,7 +495,7 @@ static bool buildMUBUFOffsetLoadStore(const SIInstrInfo *TII,
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return false;
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const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata);
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BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
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MachineInstrBuilder NewMI = BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
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.add(*Reg)
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.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc))
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.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset))
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@ -488,6 +504,11 @@ static bool buildMUBUFOffsetLoadStore(const SIInstrInfo *TII,
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.addImm(0) // slc
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.addImm(0) // tfe
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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const MachineOperand *VDataIn = TII->getNamedOperand(*MI,
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AMDGPU::OpName::vdata_in);
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if (VDataIn)
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NewMI.add(*VDataIn);
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return true;
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}
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; GCN-LABEL: {{^}}load_local_hi_v2i16_undeflo:
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; GCN: s_waitcnt
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@ -503,6 +503,62 @@ entry:
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ret void
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}
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; Local object gives known offset, so requires converting from offen
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; to offset variant.
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; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_to_offset:
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4094
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define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i16], align 2
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025
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%load = load i16, i16* %gep
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%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
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%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
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store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8_to_offset:
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
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define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i8], align 2
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
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%load = load i8, i8* %gep
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%ext = sext i8 %load to i16
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%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
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%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
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store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8_to_offset:
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
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define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i8], align 2
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
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%load = load i8, i8* %gep
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%ext = zext i8 %load to i16
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%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
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%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
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store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
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ret void
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}
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; FIXME: Remove m0 init and waitcnt between reads
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; FIXME: Is there a cost to using the extload over not?
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; GCN-LABEL: {{^}}load_local_v2i16_split:
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; GCN-LABEL: {{^}}load_local_lo_v2i16_undeflo:
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; GCN: s_waitcnt
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@ -588,4 +588,63 @@ entry:
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ret void
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}
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; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_to_offset:
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094
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; VI: buffer_load_ushort v
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define void @load_private_lo_v2i16_reglo_vreg_to_offset(i32 %reg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i16], align 2
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%reg.bc = bitcast i32 %reg to <2 x i16>
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025
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%load = load volatile i16, i16* %gep
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%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
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store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s5 offset:4095
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; VI: buffer_load_sbyte v
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define void @load_private_lo_v2i16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i8], align 2
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%reg.bc = bitcast i32 %reg to <2 x i16>
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
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%load = load volatile i8, i8* %gep
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%load.ext = sext i8 %load to i16
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%build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0
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store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s5 offset:4095
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; VI: buffer_load_ubyte v
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define void @load_private_lo_v2i16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i8], align 2
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%reg.bc = bitcast i32 %reg to <2 x i16>
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
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%load = load volatile i8, i8* %gep
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%load.ext = zext i8 %load to i16
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%build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0
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store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; GCN-LABEL: {{^}}store_global_hi_v2i16:
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; GCN: s_waitcnt
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@ -591,4 +591,39 @@ entry:
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ret void
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}
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; GCN-LABEL: {{^}}store_private_hi_v2i16_to_offset:
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; GCN: s_waitcnt
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094
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define void @store_private_hi_v2i16_to_offset(i32 %arg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i16], align 2
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%value = bitcast i32 %arg to <2 x i16>
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%hi = extractelement <2 x i16> %value, i32 1
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%gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025
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store i16 %hi, i16* %gep
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ret void
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}
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; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_to_offset:
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; GCN: s_waitcnt
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; GFX9: buffer_store_dword
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; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s5 offset:4095
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define void @store_private_hi_v2i16_i8_to_offset(i32 %arg) #0 {
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entry:
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%obj0 = alloca [10 x i32], align 4
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%obj1 = alloca [4096 x i8], align 2
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%bc = bitcast [10 x i32]* %obj0 to i32*
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store volatile i32 123, i32* %bc
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%value = bitcast i32 %arg to <2 x i16>
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%hi = extractelement <2 x i16> %value, i32 1
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%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
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%trunc = trunc i16 %hi to i8
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store i8 %trunc, i8* %gep
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ret void
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}
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attributes #0 = { nounwind }
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