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[InstCombine] Try to fold trunc(shuffle(zext)) to just a shuffle (#78636)

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Tries to remove extra trunc/ext instruction for shufflevector
instructions.
This commit is contained in:
Alexey Bataev 2024-01-19 09:29:01 -05:00 committed by GitHub
parent a2a0089ac3
commit 4d11f04b20
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GPG Key ID: B5690EEEBB952194
3 changed files with 14 additions and 10 deletions
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10
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
View File

@ -103,6 +103,13 @@ Value *InstCombinerImpl::EvaluateInDifferentType(Value *V, Type *Ty,
}
}
break;
case Instruction::ShuffleVector: {
Value *Op0 = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
Value *Op1 = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
Res = new ShuffleVectorInst(Op0, Op1,
cast<ShuffleVectorInst>(I)->getShuffleMask());
break;
}
default:
// TODO: Can handle more cases here.
llvm_unreachable("Unreachable!");
@ -363,6 +370,9 @@ static bool canEvaluateTruncated(Value *V, Type *Ty, InstCombinerImpl &IC,
I->getOpcode() == Instruction::FPToSI);
return Ty->getScalarSizeInBits() >= MinBitWidth;
}
case Instruction::ShuffleVector:
return canEvaluateTruncated(I->getOperand(0), Ty, IC, CxtI) &&
canEvaluateTruncated(I->getOperand(1), Ty, IC, CxtI);
default:
// TODO: Can handle more cases here.
break;

7
llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
View File

@ -671,11 +671,8 @@ define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> %
define <4 x i32> @computesignbits_through_two_input_shuffle(<4 x i32> %x, <4 x i32> %y, <4 x i1> %cond1, <4 x i1> %cond2) {
; CHECK-LABEL: @computesignbits_through_two_input_shuffle(
; CHECK-NEXT: [[SEXT1:%.*]] = sext <4 x i1> [[COND1:%.*]] to <4 x i32>
; CHECK-NEXT: [[SEXT2:%.*]] = sext <4 x i1> [[COND2:%.*]] to <4 x i32>
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i32> [[SEXT1]], <4 x i32> [[SEXT2]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[COND]] to <4 x i1>
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[COND1:%.*]], <4 x i1> [[COND2:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[COND]], <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]]
; CHECK-NEXT: ret <4 x i32> [[SEL]]
;
%sext1 = sext <4 x i1> %cond1 to <4 x i32>

7
llvm/test/Transforms/InstCombine/logical-select.ll
View File

@ -707,11 +707,8 @@ define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> %
define <4 x i32> @computesignbits_through_two_input_shuffle(<4 x i32> %x, <4 x i32> %y, <4 x i1> %cond1, <4 x i1> %cond2) {
; CHECK-LABEL: @computesignbits_through_two_input_shuffle(
; CHECK-NEXT: [[SEXT1:%.*]] = sext <4 x i1> [[COND1:%.*]] to <4 x i32>
; CHECK-NEXT: [[SEXT2:%.*]] = sext <4 x i1> [[COND2:%.*]] to <4 x i32>
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i32> [[SEXT1]], <4 x i32> [[SEXT2]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[COND]] to <4 x i1>
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]]
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[COND1:%.*]], <4 x i1> [[COND2:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[COND]], <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]]
; CHECK-NEXT: ret <4 x i32> [[SEL]]
;
%sext1 = sext <4 x i1> %cond1 to <4 x i32>