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AMDGPU/GlobalISel: Widen small uaddo/usubo
llvm-svn: 352294
This commit is contained in:
parent
00102c7d95
commit
4d47594fc5
@ -103,7 +103,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
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G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
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.legalFor({{S32, S1}});
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.legalFor({{S32, S1}})
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.clampScalar(0, S32, S32);
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getActionDefinitionsBuilder(G_BITCAST)
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.legalForCartesianProduct({S32, V2S16})
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97
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
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97
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
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@ -0,0 +1,97 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_uaddo_s32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_uaddo_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO1]](s1)
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; CHECK: $vgpr0 = COPY [[UADDO]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32), %3:_(s1) = G_UADDO %0, %1
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%4:_(s32) = G_ZEXT %3
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$vgpr0 = COPY %2
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$vgpr1 = COPY %4
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...
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---
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name: test_uaddo_s7
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_uaddo_s7
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
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; CHECK: $vgpr0 = COPY [[AND3]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s7) = G_TRUNC %0
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%3:_(s7) = G_TRUNC %1
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%4:_(s7), %5:_(s1) = G_UADDO %2, %3
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%6:_(s32) = G_ZEXT %4
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%7:_(s32) = G_ZEXT %5
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$vgpr0 = COPY %6
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$vgpr1 = COPY %7
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...
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---
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name: test_uaddo_s16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_uaddo_s16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
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; CHECK: $vgpr0 = COPY [[AND3]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(s16), %5:_(s1) = G_UADDO %2, %3
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%6:_(s32) = G_ZEXT %4
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%7:_(s32) = G_ZEXT %5
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$vgpr0 = COPY %6
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$vgpr1 = COPY %7
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...
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97
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
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97
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
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@ -0,0 +1,97 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_usubo_s32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_usubo_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBO1]](s1)
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; CHECK: $vgpr0 = COPY [[USUBO]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32), %3:_(s1) = G_USUBO %0, %1
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%4:_(s32) = G_ZEXT %3
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$vgpr0 = COPY %2
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$vgpr1 = COPY %4
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...
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---
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name: test_usubo_s7
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_usubo_s7
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
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; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
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; CHECK: $vgpr0 = COPY [[AND3]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s7) = G_TRUNC %0
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%3:_(s7) = G_TRUNC %1
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%4:_(s7), %5:_(s1) = G_USUBO %2, %3
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%6:_(s32) = G_ZEXT %4
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%7:_(s32) = G_ZEXT %5
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$vgpr0 = COPY %6
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$vgpr1 = COPY %7
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...
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---
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name: test_usubo_s16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_usubo_s16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
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; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
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; CHECK: $vgpr0 = COPY [[AND3]](s32)
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; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(s16), %5:_(s1) = G_USUBO %2, %3
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%6:_(s32) = G_ZEXT %4
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%7:_(s32) = G_ZEXT %5
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$vgpr0 = COPY %6
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$vgpr1 = COPY %7
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...
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