From 501bb982b935be79ada6d4615909dec8fb9a3fb7 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 14 Jun 2019 20:03:42 +0000 Subject: [PATCH] [x86] add test for 256-bit blendv with AVX targets; NFC This is a reduction of the pattern seen in D63233. llvm-svn: 363448 --- llvm/test/CodeGen/X86/vselect-avx.ll | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/llvm/test/CodeGen/X86/vselect-avx.ll b/llvm/test/CodeGen/X86/vselect-avx.ll index 39994f768831..8252084a1cd6 100644 --- a/llvm/test/CodeGen/X86/vselect-avx.ll +++ b/llvm/test/CodeGen/X86/vselect-avx.ll @@ -166,3 +166,43 @@ define <32 x i8> @PR22706(<32 x i1> %x) { %tmp = select <32 x i1> %x, <32 x i8> , <32 x i8> ret <32 x i8> %tmp } + +; TODO: Split a 256-bit select into two 128-bit selects when the operands are concatenated. + +define void @blendv_split(<8 x i32>* %p, <8 x i32> %cond, <8 x i32> %a, <8 x i32> %x, <8 x i32> %y, <8 x i32> %z, <8 x i32> %w) { +; AVX1-LABEL: blendv_split: +; AVX1: ## %bb.0: +; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero +; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 +; AVX1-NEXT: vpslld %xmm2, %xmm4, %xmm5 +; AVX1-NEXT: vpslld %xmm2, %xmm1, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2 +; AVX1-NEXT: vpslld %xmm3, %xmm4, %xmm4 +; AVX1-NEXT: vpslld %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1 +; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0 +; AVX1-NEXT: vmovups %ymm0, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: blendv_split: +; AVX2: ## %bb.0: +; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero +; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero +; AVX2-NEXT: vpslld %xmm2, %ymm1, %ymm2 +; AVX2-NEXT: vpslld %xmm3, %ymm1, %ymm1 +; AVX2-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0 +; AVX2-NEXT: vmovups %ymm0, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %signbits = ashr <8 x i32> %cond, + %bool = trunc <8 x i32> %signbits to <8 x i1> + %shamt1 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> zeroinitializer + %shamt2 = shufflevector <8 x i32> %y, <8 x i32> undef, <8 x i32> zeroinitializer + %sh1 = shl <8 x i32> %a, %shamt1 + %sh2 = shl <8 x i32> %a, %shamt2 + %sel = select <8 x i1> %bool, <8 x i32> %sh1, <8 x i32> %sh2 + store <8 x i32> %sel, <8 x i32>* %p, align 4 + ret void +}