From 514b3ed5361bec6b3d8d252d036711de531bb4d4 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 10 Mar 2008 18:55:53 +0000
Subject: [PATCH] fix 80 col violations.

llvm-svn: 48166
---
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 43fa1728d266..d8f9d8a7b8fb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -329,33 +329,33 @@ static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
   if (RC == PPC::GPRCRegisterClass) {
     if (SrcReg != PPC::LR) {
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
+                              .addReg(SrcReg, false, false, isKill), FrameIdx));
     } else {
       // FIXME: this spills LR immediately to memory in one step.  To do this,
       // we use R11, which we know cannot be used in the prolog/epilog.  This is
       // a hack.
       NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
-                              .addReg(PPC::R11, false, false, isKill), FrameIdx));
+                            .addReg(PPC::R11, false, false, isKill), FrameIdx));
     }
   } else if (RC == PPC::G8RCRegisterClass) {
     if (SrcReg != PPC::LR8) {
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
+                              .addReg(SrcReg, false, false, isKill), FrameIdx));
     } else {
       // FIXME: this spills LR immediately to memory in one step.  To do this,
       // we use R11, which we know cannot be used in the prolog/epilog.  This is
       // a hack.
       NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
-                              .addReg(PPC::X11, false, false, isKill), FrameIdx));
+                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
     }
   } else if (RC == PPC::F8RCRegisterClass) {
     NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
+                              .addReg(SrcReg, false, false, isKill), FrameIdx));
   } else if (RC == PPC::F4RCRegisterClass) {
     NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
+                              .addReg(SrcReg, false, false, isKill), FrameIdx));
   } else if (RC == PPC::CRRCRegisterClass) {
     if (EnablePPCRS) {  // FIXME (64-bit): Enable
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR))
@@ -374,7 +374,7 @@ static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
         unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
         // rlwinm r0, r0, ShiftBits, 0, 31.
         NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
-                         .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
+                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
       }
     
       NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
@@ -416,7 +416,7 @@ static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
     NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
                                        FrameIdx, 0, 0));
     NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
-           .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
+         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
   } else {
     assert(0 && "Unknown regclass!");
     abort();