mirror of
https://github.com/capstone-engine/llvm-capstone.git
synced 2024-11-29 08:31:13 +00:00
[COFF][ARM] Fix CodeView for Windows on 32bit ARM targets.
Create the LLVM / CodeView register mappings for the 32-bit ARM Window targets. Reviewed By: compnerd Differential Revision: https://reviews.llvm.org/D89622
This commit is contained in:
Luqman Aden
parent
7e9411efcf
commit
51892a42da
@ -15,6 +15,7 @@
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#endif
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#if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) && \
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!defined(CV_REGISTERS_ARM) && \
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!defined(CV_REGISTERS_ARM64)
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#error Need include at least one register set.
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#endif
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@ -393,13 +394,46 @@ CV_REGISTER(ARM_PC, 25)
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// Status register
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CV_REGISTER(ARM_CPSR, 25)
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CV_REGISTER(ARM_CPSR, 26)
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// ARM VFPv1 registers
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CV_REGISTER(ARM_FPSCR, 40)
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CV_REGISTER(ARM_FPEXC, 41)
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CV_REGISTER(ARM_FS0, 50)
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CV_REGISTER(ARM_FS1, 51)
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CV_REGISTER(ARM_FS2, 52)
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CV_REGISTER(ARM_FS3, 53)
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CV_REGISTER(ARM_FS4, 54)
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CV_REGISTER(ARM_FS5, 55)
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CV_REGISTER(ARM_FS6, 56)
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CV_REGISTER(ARM_FS7, 57)
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CV_REGISTER(ARM_FS8, 58)
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CV_REGISTER(ARM_FS9, 59)
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CV_REGISTER(ARM_FS10, 60)
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CV_REGISTER(ARM_FS11, 61)
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CV_REGISTER(ARM_FS12, 62)
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CV_REGISTER(ARM_FS13, 63)
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CV_REGISTER(ARM_FS14, 64)
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CV_REGISTER(ARM_FS15, 65)
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CV_REGISTER(ARM_FS16, 66)
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CV_REGISTER(ARM_FS17, 67)
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CV_REGISTER(ARM_FS18, 68)
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CV_REGISTER(ARM_FS19, 69)
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CV_REGISTER(ARM_FS20, 70)
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CV_REGISTER(ARM_FS21, 71)
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CV_REGISTER(ARM_FS22, 72)
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CV_REGISTER(ARM_FS23, 73)
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CV_REGISTER(ARM_FS24, 74)
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CV_REGISTER(ARM_FS25, 75)
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CV_REGISTER(ARM_FS26, 76)
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CV_REGISTER(ARM_FS27, 77)
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CV_REGISTER(ARM_FS28, 78)
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CV_REGISTER(ARM_FS29, 79)
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CV_REGISTER(ARM_FS30, 80)
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CV_REGISTER(ARM_FS31, 81)
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// ARM VFPv3/NEON registers
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CV_REGISTER(ARM_FS32, 200)
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@ -126,7 +126,9 @@ static CPUType mapArchToCVCPUType(Triple::ArchType Type) {
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case Triple::ArchType::x86_64:
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return CPUType::X64;
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case Triple::ArchType::thumb:
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return CPUType::Thumb;
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// LLVM currently doesn't support Windows CE and so thumb
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// here is indiscriminately mapped to ARMNT specifically.
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return CPUType::ARMNT;
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case Triple::ArchType::aarch64:
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return CPUType::ARM64;
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default:
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@ -39,6 +39,14 @@ static const EnumEntry<uint16_t> RegisterNames_X86[] = {
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#undef CV_REGISTERS_X86
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};
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static const EnumEntry<uint16_t> RegisterNames_ARM[] = {
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#define CV_REGISTERS_ARM
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#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
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#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
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#undef CV_REGISTER
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#undef CV_REGISTERS_ARM
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};
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static const EnumEntry<uint16_t> RegisterNames_ARM64[] = {
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#define CV_REGISTERS_ARM64
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#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
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@ -434,7 +442,9 @@ ArrayRef<EnumEntry<TypeLeafKind>> getTypeLeafNames() {
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}
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ArrayRef<EnumEntry<uint16_t>> getRegisterNames(CPUType Cpu) {
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if (Cpu == CPUType::ARM64) {
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if (Cpu == CPUType::ARMNT) {
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return makeArrayRef(RegisterNames_ARM);
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} else if (Cpu == CPUType::ARM64) {
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return makeArrayRef(RegisterNames_ARM64);
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}
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return makeArrayRef(RegisterNames_X86);
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@ -118,7 +118,21 @@ raw_ostream &llvm::pdb::operator<<(raw_ostream &OS, const PDB_DataKind &Data) {
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raw_ostream &llvm::pdb::operator<<(raw_ostream &OS,
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const llvm::codeview::CPURegister &CpuReg) {
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if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
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if (CpuReg.Cpu == llvm::codeview::CPUType::ARMNT) {
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switch (CpuReg.Reg) {
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#define CV_REGISTERS_ARM
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#define CV_REGISTER(name, val) \
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case codeview::RegisterId::name: \
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OS << #name; \
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return OS;
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#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
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#undef CV_REGISTER
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#undef CV_REGISTERS_ARM
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default:
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break;
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}
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} else if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
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switch (CpuReg.Reg) {
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#define CV_REGISTERS_ARM64
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#define CV_REGISTER(name, val) \
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@ -147,7 +147,30 @@ void ScalarEnumerationTraits<CPUType>::enumeration(IO &io, CPUType &Cpu) {
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}
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void ScalarEnumerationTraits<RegisterId>::enumeration(IO &io, RegisterId &Reg) {
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auto RegNames = getRegisterNames(CPUType::X64);
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const auto *Header = static_cast<COFF::header *>(io.getContext());
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assert(Header && "The IO context is not initialized");
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Optional<CPUType> CpuType;
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ArrayRef<EnumEntry<uint16_t>> RegNames;
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switch (Header->Machine) {
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case COFF::IMAGE_FILE_MACHINE_I386:
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CpuType = CPUType::Pentium3;
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break;
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case COFF::IMAGE_FILE_MACHINE_AMD64:
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CpuType = CPUType::X64;
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break;
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case COFF::IMAGE_FILE_MACHINE_ARMNT:
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CpuType = CPUType::ARMNT;
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break;
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case COFF::IMAGE_FILE_MACHINE_ARM64:
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CpuType = CPUType::ARM64;
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break;
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}
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if (CpuType)
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RegNames = getRegisterNames(*CpuType);
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for (const auto &E : RegNames) {
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io.enumCase(Reg, E.Name.str().c_str(), static_cast<RegisterId>(E.Value));
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}
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@ -55,7 +55,9 @@
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using namespace llvm;
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ARMBaseRegisterInfo::ARMBaseRegisterInfo()
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: ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
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: ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {
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ARM_MC::initLLVMToCVRegMapping(this);
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}
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static unsigned getFramePointerReg(const ARMSubtarget &STI) {
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return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
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@ -87,6 +87,7 @@ void ARMCOFFMCAsmInfoMicrosoft::anchor() { }
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ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() {
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AlignmentIsInBytes = false;
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SupportsDebugInformation = true;
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ExceptionsType = ExceptionHandling::WinEH;
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PrivateGlobalPrefix = "$M";
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PrivateLabelPrefix = "$M";
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@ -16,6 +16,7 @@
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#include "ARMMCAsmInfo.h"
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#include "TargetInfo/ARMTargetInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/DebugInfo/CodeView/CodeView.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCELFStreamer.h"
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@ -205,9 +206,120 @@ static MCInstrInfo *createARMMCInstrInfo() {
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return X;
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}
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void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
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// Mapping from CodeView to MC register id.
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static const struct {
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codeview::RegisterId CVReg;
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MCPhysReg Reg;
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} RegMap[] = {
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{codeview::RegisterId::ARM_R0, ARM::R0},
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{codeview::RegisterId::ARM_R1, ARM::R1},
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{codeview::RegisterId::ARM_R2, ARM::R2},
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{codeview::RegisterId::ARM_R3, ARM::R3},
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{codeview::RegisterId::ARM_R4, ARM::R4},
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{codeview::RegisterId::ARM_R5, ARM::R5},
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{codeview::RegisterId::ARM_R6, ARM::R6},
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{codeview::RegisterId::ARM_R7, ARM::R7},
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{codeview::RegisterId::ARM_R8, ARM::R8},
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{codeview::RegisterId::ARM_R9, ARM::R9},
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{codeview::RegisterId::ARM_R10, ARM::R10},
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{codeview::RegisterId::ARM_R11, ARM::R11},
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{codeview::RegisterId::ARM_R12, ARM::R12},
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{codeview::RegisterId::ARM_SP, ARM::SP},
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{codeview::RegisterId::ARM_LR, ARM::LR},
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{codeview::RegisterId::ARM_PC, ARM::PC},
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{codeview::RegisterId::ARM_CPSR, ARM::CPSR},
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{codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
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{codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
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{codeview::RegisterId::ARM_FS0, ARM::S0},
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{codeview::RegisterId::ARM_FS1, ARM::S1},
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{codeview::RegisterId::ARM_FS2, ARM::S2},
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{codeview::RegisterId::ARM_FS3, ARM::S3},
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{codeview::RegisterId::ARM_FS4, ARM::S4},
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{codeview::RegisterId::ARM_FS5, ARM::S5},
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{codeview::RegisterId::ARM_FS6, ARM::S6},
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{codeview::RegisterId::ARM_FS7, ARM::S7},
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{codeview::RegisterId::ARM_FS8, ARM::S8},
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{codeview::RegisterId::ARM_FS9, ARM::S9},
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{codeview::RegisterId::ARM_FS10, ARM::S10},
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{codeview::RegisterId::ARM_FS11, ARM::S11},
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{codeview::RegisterId::ARM_FS12, ARM::S12},
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{codeview::RegisterId::ARM_FS13, ARM::S13},
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{codeview::RegisterId::ARM_FS14, ARM::S14},
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{codeview::RegisterId::ARM_FS15, ARM::S15},
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{codeview::RegisterId::ARM_FS16, ARM::S16},
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{codeview::RegisterId::ARM_FS17, ARM::S17},
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{codeview::RegisterId::ARM_FS18, ARM::S18},
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{codeview::RegisterId::ARM_FS19, ARM::S19},
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{codeview::RegisterId::ARM_FS20, ARM::S20},
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{codeview::RegisterId::ARM_FS21, ARM::S21},
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{codeview::RegisterId::ARM_FS22, ARM::S22},
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{codeview::RegisterId::ARM_FS23, ARM::S23},
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{codeview::RegisterId::ARM_FS24, ARM::S24},
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{codeview::RegisterId::ARM_FS25, ARM::S25},
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{codeview::RegisterId::ARM_FS26, ARM::S26},
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{codeview::RegisterId::ARM_FS27, ARM::S27},
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{codeview::RegisterId::ARM_FS28, ARM::S28},
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{codeview::RegisterId::ARM_FS29, ARM::S29},
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{codeview::RegisterId::ARM_FS30, ARM::S30},
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{codeview::RegisterId::ARM_FS31, ARM::S31},
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{codeview::RegisterId::ARM_ND0, ARM::D0},
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{codeview::RegisterId::ARM_ND1, ARM::D1},
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{codeview::RegisterId::ARM_ND2, ARM::D2},
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{codeview::RegisterId::ARM_ND3, ARM::D3},
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{codeview::RegisterId::ARM_ND4, ARM::D4},
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{codeview::RegisterId::ARM_ND5, ARM::D5},
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{codeview::RegisterId::ARM_ND6, ARM::D6},
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{codeview::RegisterId::ARM_ND7, ARM::D7},
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{codeview::RegisterId::ARM_ND8, ARM::D8},
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{codeview::RegisterId::ARM_ND9, ARM::D9},
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{codeview::RegisterId::ARM_ND10, ARM::D10},
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{codeview::RegisterId::ARM_ND11, ARM::D11},
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{codeview::RegisterId::ARM_ND12, ARM::D12},
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{codeview::RegisterId::ARM_ND13, ARM::D13},
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{codeview::RegisterId::ARM_ND14, ARM::D14},
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{codeview::RegisterId::ARM_ND15, ARM::D15},
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{codeview::RegisterId::ARM_ND16, ARM::D16},
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{codeview::RegisterId::ARM_ND17, ARM::D17},
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{codeview::RegisterId::ARM_ND18, ARM::D18},
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{codeview::RegisterId::ARM_ND19, ARM::D19},
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{codeview::RegisterId::ARM_ND20, ARM::D20},
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{codeview::RegisterId::ARM_ND21, ARM::D21},
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{codeview::RegisterId::ARM_ND22, ARM::D22},
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{codeview::RegisterId::ARM_ND23, ARM::D23},
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{codeview::RegisterId::ARM_ND24, ARM::D24},
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{codeview::RegisterId::ARM_ND25, ARM::D25},
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{codeview::RegisterId::ARM_ND26, ARM::D26},
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{codeview::RegisterId::ARM_ND27, ARM::D27},
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{codeview::RegisterId::ARM_ND28, ARM::D28},
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{codeview::RegisterId::ARM_ND29, ARM::D29},
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{codeview::RegisterId::ARM_ND30, ARM::D30},
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{codeview::RegisterId::ARM_ND31, ARM::D31},
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{codeview::RegisterId::ARM_NQ0, ARM::Q0},
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{codeview::RegisterId::ARM_NQ1, ARM::Q1},
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{codeview::RegisterId::ARM_NQ2, ARM::Q2},
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{codeview::RegisterId::ARM_NQ3, ARM::Q3},
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{codeview::RegisterId::ARM_NQ4, ARM::Q4},
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{codeview::RegisterId::ARM_NQ5, ARM::Q5},
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{codeview::RegisterId::ARM_NQ6, ARM::Q6},
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{codeview::RegisterId::ARM_NQ7, ARM::Q7},
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{codeview::RegisterId::ARM_NQ8, ARM::Q8},
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{codeview::RegisterId::ARM_NQ9, ARM::Q9},
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{codeview::RegisterId::ARM_NQ10, ARM::Q10},
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{codeview::RegisterId::ARM_NQ11, ARM::Q11},
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{codeview::RegisterId::ARM_NQ12, ARM::Q12},
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{codeview::RegisterId::ARM_NQ13, ARM::Q13},
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{codeview::RegisterId::ARM_NQ14, ARM::Q14},
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{codeview::RegisterId::ARM_NQ15, ARM::Q15},
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};
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for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
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MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
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}
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static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
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ARM_MC::initLLVMToCVRegMapping(X);
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return X;
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}
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@ -41,6 +41,7 @@ class raw_pwrite_stream;
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namespace ARM_MC {
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std::string ParseARMTriple(const Triple &TT, StringRef CPU);
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void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
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bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
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167
llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll
Normal file
167
llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll
Normal file
@ -0,0 +1,167 @@
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; RUN: llc < %s -filetype=obj | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ
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; Generated from:
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; volatile int x;
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; int getint(void);
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; void putint(int);
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; static inline int inlineinc(int a) {
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; int b = a + 1;
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; ++x;
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; return b;
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; }
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; void f(int p) {
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; if (p) {
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; int a = getint();
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; int b = inlineinc(a);
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; putint(b);
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; } else {
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; int c = getint();
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; putint(c);
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; }
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; }
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; OBJ: Compile3Sym {
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; OBJ-NEXT: Kind: S_COMPILE3 (0x113C)
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; OBJ-NEXT: Language: C (0x0)
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; OBJ-NEXT: Flags [ (0x0)
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; OBJ-NEXT: ]
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; OBJ-NEXT: Machine: ARMNT (0xF4)
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; OBJ: LocalSym {
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; OBJ-NEXT: Kind: S_LOCAL (0x113E)
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; OBJ-NEXT: Type: int (0x74)
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; OBJ-NEXT: Flags [ (0x1)
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; OBJ-NEXT: IsParameter (0x1)
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; OBJ-NEXT: ]
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; OBJ-NEXT: VarName: p
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; OBJ-NEXT: }
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; OBJ-NEXT: DefRangeRegisterRelSym {
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; OBJ-NEXT: Kind: S_DEFRANGE_REGISTER_REL (0x1145)
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; OBJ-NEXT: BaseRegister: ARM_SP (0x17)
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; OBJ-NEXT: HasSpilledUDTMember: No
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; OBJ-NEXT: OffsetInParent: 0
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; OBJ-NEXT: BasePointerOffset: 12
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; OBJ-NEXT: LocalVariableAddrRange {
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; OBJ-NEXT: OffsetStart: .text+0x8
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; OBJ-NEXT: ISectStart: 0x0
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; OBJ-NEXT: Range: 0x1A
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; OBJ-NEXT: }
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; OBJ-NEXT: }
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; ModuleID = 'test.c'
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source_filename = "test.c"
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target datalayout = "e-m:w-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7-pc-windows-msvc19.11.0"
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@x = dso_local global i32 0, align 4, !dbg !0
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; Function Attrs: noinline nounwind optnone
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define dso_local arm_aapcs_vfpcc void @f(i32 %p) !dbg !14 {
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entry:
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%p.addr = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 %p, i32* %p.addr, align 4
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call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !17, metadata !DIExpression()), !dbg !18
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%0 = load i32, i32* %p.addr, align 4, !dbg !19
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%tobool = icmp ne i32 %0, 0, !dbg !19
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br i1 %tobool, label %if.then, label %if.else, !dbg !19
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|
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if.then: ; preds = %entry
|
||||
call void @llvm.dbg.declare(metadata i32* %a, metadata !20, metadata !DIExpression()), !dbg !23
|
||||
%call = call arm_aapcs_vfpcc i32 @getint(), !dbg !23
|
||||
store i32 %call, i32* %a, align 4, !dbg !23
|
||||
call void @llvm.dbg.declare(metadata i32* %b, metadata !24, metadata !DIExpression()), !dbg !25
|
||||
%1 = load i32, i32* %a, align 4, !dbg !25
|
||||
%call1 = call arm_aapcs_vfpcc i32 @inlineinc(i32 %1), !dbg !25
|
||||
store i32 %call1, i32* %b, align 4, !dbg !25
|
||||
%2 = load i32, i32* %b, align 4, !dbg !26
|
||||
call arm_aapcs_vfpcc void @putint(i32 %2), !dbg !26
|
||||
br label %if.end, !dbg !27
|
||||
|
||||
if.else: ; preds = %entry
|
||||
call void @llvm.dbg.declare(metadata i32* %c, metadata !28, metadata !DIExpression()), !dbg !30
|
||||
%call2 = call arm_aapcs_vfpcc i32 @getint(), !dbg !30
|
||||
store i32 %call2, i32* %c, align 4, !dbg !30
|
||||
%3 = load i32, i32* %c, align 4, !dbg !31
|
||||
call arm_aapcs_vfpcc void @putint(i32 %3), !dbg !31
|
||||
br label %if.end, !dbg !32
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
ret void, !dbg !33
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone speculatable willreturn
|
||||
declare void @llvm.dbg.declare(metadata, metadata, metadata)
|
||||
|
||||
declare dso_local arm_aapcs_vfpcc i32 @getint()
|
||||
|
||||
; Function Attrs: noinline nounwind optnone
|
||||
define internal arm_aapcs_vfpcc i32 @inlineinc(i32 %a) !dbg !34 {
|
||||
entry:
|
||||
%a.addr = alloca i32, align 4
|
||||
%b = alloca i32, align 4
|
||||
store i32 %a, i32* %a.addr, align 4
|
||||
call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !37, metadata !DIExpression()), !dbg !38
|
||||
call void @llvm.dbg.declare(metadata i32* %b, metadata !39, metadata !DIExpression()), !dbg !40
|
||||
%0 = load i32, i32* %a.addr, align 4, !dbg !40
|
||||
%add = add nsw i32 %0, 1, !dbg !40
|
||||
store i32 %add, i32* %b, align 4, !dbg !40
|
||||
%1 = load volatile i32, i32* @x, align 4, !dbg !41
|
||||
%inc = add nsw i32 %1, 1, !dbg !41
|
||||
store volatile i32 %inc, i32* @x, align 4, !dbg !41
|
||||
%2 = load i32, i32* %b, align 4, !dbg !42
|
||||
ret i32 %2, !dbg !42
|
||||
}
|
||||
|
||||
declare dso_local arm_aapcs_vfpcc void @putint(i32)
|
||||
|
||||
!llvm.dbg.cu = !{!2}
|
||||
!llvm.module.flags = !{!9, !10, !11, !12}
|
||||
!llvm.ident = !{!13}
|
||||
|
||||
!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
|
||||
!1 = distinct !DIGlobalVariable(name: "x", scope: !2, file: !6, line: 1, type: !7, isLocal: false, isDefinition: true)
|
||||
!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 12.0.0 (https://github.com/llvm/llvm-project.git fc031d29bea856f2b91a250fd81c5f9fb79dbe07)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: None)
|
||||
!3 = !DIFile(filename: "F:\\tmp\\test.c", directory: "F:\\tmp", checksumkind: CSK_MD5, checksum: "5fbd15e58dd6931fc3081de308d52889")
|
||||
!4 = !{}
|
||||
!5 = !{!0}
|
||||
!6 = !DIFile(filename: "test.c", directory: "F:\\tmp", checksumkind: CSK_MD5, checksum: "5fbd15e58dd6931fc3081de308d52889")
|
||||
!7 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !8)
|
||||
!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
|
||||
!9 = !{i32 2, !"CodeView", i32 1}
|
||||
!10 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!11 = !{i32 1, !"wchar_size", i32 2}
|
||||
!12 = !{i32 1, !"min_enum_size", i32 4}
|
||||
!13 = !{!"clang version 12.0.0 (https://github.com/llvm/llvm-project.git fc031d29bea856f2b91a250fd81c5f9fb79dbe07)"}
|
||||
!14 = distinct !DISubprogram(name: "f", scope: !6, file: !6, line: 9, type: !15, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !4)
|
||||
!15 = !DISubroutineType(types: !16)
|
||||
!16 = !{null, !8}
|
||||
!17 = !DILocalVariable(name: "p", arg: 1, scope: !14, file: !6, line: 9, type: !8)
|
||||
!18 = !DILocation(line: 9, scope: !14)
|
||||
!19 = !DILocation(line: 10, scope: !14)
|
||||
!20 = !DILocalVariable(name: "a", scope: !21, file: !6, line: 11, type: !8)
|
||||
!21 = distinct !DILexicalBlock(scope: !22, file: !6, line: 10)
|
||||
!22 = distinct !DILexicalBlock(scope: !14, file: !6, line: 10)
|
||||
!23 = !DILocation(line: 11, scope: !21)
|
||||
!24 = !DILocalVariable(name: "b", scope: !21, file: !6, line: 12, type: !8)
|
||||
!25 = !DILocation(line: 12, scope: !21)
|
||||
!26 = !DILocation(line: 13, scope: !21)
|
||||
!27 = !DILocation(line: 14, scope: !21)
|
||||
!28 = !DILocalVariable(name: "c", scope: !29, file: !6, line: 15, type: !8)
|
||||
!29 = distinct !DILexicalBlock(scope: !22, file: !6, line: 14)
|
||||
!30 = !DILocation(line: 15, scope: !29)
|
||||
!31 = !DILocation(line: 16, scope: !29)
|
||||
!32 = !DILocation(line: 17, scope: !29)
|
||||
!33 = !DILocation(line: 18, scope: !14)
|
||||
!34 = distinct !DISubprogram(name: "inlineinc", scope: !6, file: !6, line: 4, type: !35, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !4)
|
||||
!35 = !DISubroutineType(types: !36)
|
||||
!36 = !{!8, !8}
|
||||
!37 = !DILocalVariable(name: "a", arg: 1, scope: !34, file: !6, line: 4, type: !8)
|
||||
!38 = !DILocation(line: 4, scope: !34)
|
||||
!39 = !DILocalVariable(name: "b", scope: !34, file: !6, line: 5, type: !8)
|
||||
!40 = !DILocation(line: 5, scope: !34)
|
||||
!41 = !DILocation(line: 6, scope: !34)
|
||||
!42 = !DILocation(line: 7, scope: !34)
|
||||
3
llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg
Normal file
3
llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg
Normal file
@ -0,0 +1,3 @@
|
||||
if not 'ARM' in config.root.targets:
|
||||
config.unsupported = True
|
||||
|
||||
@ -288,7 +288,18 @@ static std::string formatCookieKind(FrameCookieKind Kind) {
|
||||
}
|
||||
|
||||
static std::string formatRegisterId(RegisterId Id, CPUType Cpu) {
|
||||
if (Cpu == CPUType::ARM64) {
|
||||
if (Cpu == CPUType::ARMNT) {
|
||||
switch (Id) {
|
||||
#define CV_REGISTERS_ARM
|
||||
#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
|
||||
#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
|
||||
#undef CV_REGISTER
|
||||
#undef CV_REGISTERS_ARM
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else if (Cpu == CPUType::ARM64) {
|
||||
switch (Id) {
|
||||
#define CV_REGISTERS_ARM64
|
||||
#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user