Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-10-07 10:54:01 +00:00
Code Issues Actions 4 Packages Projects Releases Wiki Activity

Add XCore intrinsic for crc32.

Browse Source 
llvm-svn: 132336
This commit is contained in:
Richard Osborne 2011-05-31 14:47:36 +00:00
parent 36d027f7f6
commit 542f9a2bcf
4 changed files with 25 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/include/llvm/IntrinsicsXCore.td
View File

@ -11,6 +11,7 @@
let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
// Miscellaneous instructions.
def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>;
def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;

8
llvm/lib/Target/XCore/XCoreInstrInfo.td
View File

@ -472,7 +472,13 @@ def REMU_l3r : FL3R<"remu", urem>;
}
def XOR_l3r : FL3R<"xor", xor>;
defm ASHR : FL3R_L2RBITP<"ashr", sra>;
// TODO crc32, crc8, inpw, outpw
let Constraints = "$src1 = $dst" in
def CRC_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"crc32 $dst, $src2, $src3",
[(set GRRegs:$dst, (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, GRRegs:$src3))]>;
// TODO inpw, outpw
let mayStore=1 in {
def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
"st16 $val, $addr[$offset]",

9
llvm/test/CodeGen/XCore/bitrev.ll
View File

@ -1,9 +0,0 @@
; RUN: llc < %s -march=xcore | FileCheck %s
declare i32 @llvm.xcore.bitrev(i32)
define i32 @bitrev(i32 %val) {
; CHECK: bitrev:
; CHECK: bitrev r0, r0
%result = call i32 @llvm.xcore.bitrev(i32 %val)
ret i32 %result
}

17
llvm/test/CodeGen/XCore/misc-intrinsics.ll Normal file
View File

@ -0,0 +1,17 @@
; RUN: llc < %s -march=xcore | FileCheck %s
declare i32 @llvm.xcore.bitrev(i32)
declare i32 @llvm.xcore.crc32(i32, i32, i32)
define i32 @bitrev(i32 %val) {
; CHECK: bitrev:
; CHECK: bitrev r0, r0
%result = call i32 @llvm.xcore.bitrev(i32 %val)
ret i32 %result
}
define i32 @crc32(i32 %crc, i32 %data, i32 %poly) {
; CHECK: crc32:
; CHECK: crc32 r0, r1, r2
%result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly)
ret i32 %result
}