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[AVX-512] Allow legacy scalar min/max intrinsics to select EVEX instructions when available
This patch introduces new X86ISD::FMAXS and X86ISD::FMINS opcodes. The legacy intrinsics now lower to this node. As do the AVX-512 masked intrinsics when the rounding mode is CUR_DIRECTION. I've merged a copy of the tablegen multiclass avx512_fp_scalar into avx512_fp_scalar_sae. avx512_fp_scalar still needs to support CUR_DIRECTION appearing as a rounding mode for X86ISD::FADD_ROUND and others. Differential revision: https://reviews.llvm.org/D30186 llvm-svn: 295810
This commit is contained in:
Craig Topper
parent
5cd6c5cacf
commit
56d4022997
@ -18991,6 +18991,14 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget &Subtarget
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SDValue Src2 = Op.getOperand(2);
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SDValue passThru = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
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if (IntrWithRoundingModeOpcode != 0) {
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SDValue Rnd = Op.getOperand(5);
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if (!isRoundModeCurDirection(Rnd))
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return getScalarMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, VT, Src1, Src2, Rnd),
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Mask, passThru, Subtarget, DAG);
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}
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
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Mask, passThru, Subtarget, DAG);
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}
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@ -23910,8 +23918,10 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::ABS: return "X86ISD::ABS";
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case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
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case X86ISD::FMAX: return "X86ISD::FMAX";
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case X86ISD::FMAXS: return "X86ISD::FMAXS";
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case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
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case X86ISD::FMIN: return "X86ISD::FMIN";
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case X86ISD::FMINS: return "X86ISD::FMINS";
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case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
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case X86ISD::FMAXC: return "X86ISD::FMAXC";
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case X86ISD::FMINC: return "X86ISD::FMINC";
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@ -251,6 +251,9 @@ namespace llvm {
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/// Commutative FMIN and FMAX.
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FMAXC, FMINC,
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/// Scalar intrinsic floating point max and min.
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FMAXS, FMINS,
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/// Floating point reciprocal-sqrt and reciprocal approximation.
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/// Note that these typically require refinement
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/// in order to obtain suitable precision.
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@ -4195,13 +4195,43 @@ multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo
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EVEX_B, EVEX_RC;
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}
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multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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SDNode VecNode, OpndItins itins, bit IsCommutable> {
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let ExeDomain = _.ExeDomain in
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SDNode OpNode, SDNode VecNode, SDNode SaeNode,
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OpndItins itins, bit IsCommutable> {
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let ExeDomain = _.ExeDomain in {
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defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (VecNode _.RC:$src1, _.RC:$src2)),
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itins.rr>;
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defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (VecNode _.RC:$src1,
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_.ScalarIntMemCPat:$src2)),
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itins.rm>;
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let isCodeGenOnly = 1, Predicates = [HasAVX512] in {
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def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.FRC:$src2),
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OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
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itins.rr> {
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let isCommutable = IsCommutable;
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}
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def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.ScalarMemOp:$src2),
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OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.FRC:$dst, (OpNode _.FRC:$src1,
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(_.ScalarLdFrag addr:$src2)))], itins.rm>;
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}
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defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"{sae}, $src2, $src1", "$src1, $src2, {sae}",
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(VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 FROUND_NO_EXC))>, EVEX_B;
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}
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}
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multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -4220,25 +4250,23 @@ multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SDNode VecNode,
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SDNode VecNode, SDNode SaeNode,
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SizeItins itins, bit IsCommutable> {
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defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
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itins.s, IsCommutable>,
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avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
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itins.s, IsCommutable>,
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defm SSZ : avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, OpNode,
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VecNode, SaeNode, itins.s, IsCommutable>,
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XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
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itins.d, IsCommutable>,
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avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
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itins.d, IsCommutable>,
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defm SDZ : avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, OpNode,
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VecNode, SaeNode, itins.d, IsCommutable>,
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XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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}
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defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
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defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_MUL_ITINS_S, 1>;
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defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
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defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_DIV_ITINS_S, 0>;
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defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 0>;
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defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 0>;
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defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fmins, X86fminRnd,
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SSE_ALU_ITINS_S, 0>;
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defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxRnd,
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SSE_ALU_ITINS_S, 0>;
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// MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use
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// X86fminc and X86fmaxc instead of X86fmin and X86fmax
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@ -455,7 +455,7 @@ class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm,
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Domain d = GenericDomain>
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: I<o, F, outs, ins, asm, pattern, itin, d> {
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let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
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!if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
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!if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
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!if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
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!if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
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!if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
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@ -42,6 +42,8 @@ def SDTX86CmpTestSae : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>;
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def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>;
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// Commutative and Associative FMIN and FMAX.
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def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
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@ -259,8 +259,8 @@ multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
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/// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
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multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr,
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SDPatternOperator Int, RegisterClass RC,
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string asm, Operand memopr,
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SDPatternOperator OpNode, RegisterClass RC,
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ValueType VT, string asm, Operand memopr,
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ComplexPattern mem_cpat, Domain d,
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OpndItins itins, bit Is2Addr = 1> {
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let isCodeGenOnly = 1, hasSideEffects = 0 in {
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@ -268,14 +268,14 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in {
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr, d>,
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[(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
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Sched<[itins.Sched]>;
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let mayLoad = 1 in
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def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (Int RC:$src1, mem_cpat:$src2))], itins.rm, d>,
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[(set RC:$dst, (VT (OpNode RC:$src1, mem_cpat:$src2)))], itins.rm, d>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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@ -3047,21 +3047,20 @@ multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
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SDPatternOperator IntSS,
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SDPatternOperator IntSD,
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SDPatternOperator OpNode,
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SizeItins itins> {
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defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, IntSS, VR128,
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defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, OpNode, VR128, v4f32,
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!strconcat(OpcodeStr, "ss"), ssmem, sse_load_f32,
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SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG, VEX_WIG;
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defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, IntSD, VR128,
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defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, OpNode, VR128, v2f64,
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!strconcat(OpcodeStr, "sd"), sdmem, sse_load_f64,
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SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG, VEX_WIG;
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let Constraints = "$src1 = $dst" in {
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defm SS : sse12_fp_scalar_int<opc, OpcodeStr, IntSS, VR128,
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defm SS : sse12_fp_scalar_int<opc, OpcodeStr, OpNode, VR128, v4f32,
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!strconcat(OpcodeStr, "ss"), ssmem, sse_load_f32,
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SSEPackedSingle, itins.s>, XS;
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defm SD : sse12_fp_scalar_int<opc, OpcodeStr, IntSD, VR128,
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defm SD : sse12_fp_scalar_int<opc, OpcodeStr, OpNode, VR128, v2f64,
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!strconcat(OpcodeStr, "sd"), sdmem, sse_load_f64,
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SSEPackedDouble, itins.d>, XD;
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}
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@ -3070,29 +3069,23 @@ multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
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// Binary Arithmetic instructions
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defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x58, "add", null_frag, null_frag,
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SSE_ALU_ITINS_S>;
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basic_sse12_fp_binop_s_int<0x58, "add", null_frag, SSE_ALU_ITINS_S>;
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defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
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basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x59, "mul", null_frag, null_frag,
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SSE_MUL_ITINS_S>;
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basic_sse12_fp_binop_s_int<0x59, "mul", null_frag, SSE_MUL_ITINS_S>;
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let isCommutable = 0 in {
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defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5C, "sub", null_frag, null_frag,
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SSE_ALU_ITINS_S>;
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basic_sse12_fp_binop_s_int<0x5C, "sub", null_frag,SSE_ALU_ITINS_S>;
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defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
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basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5E, "div", null_frag, null_frag,
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SSE_DIV_ITINS_S>;
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basic_sse12_fp_binop_s_int<0x5E, "div", null_frag,SSE_DIV_ITINS_S>;
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defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5F, "max", int_x86_sse_max_ss,
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int_x86_sse2_max_sd, SSE_ALU_ITINS_S>;
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basic_sse12_fp_binop_s_int<0x5F, "max", X86fmaxs, SSE_ALU_ITINS_S>;
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defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
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basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
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basic_sse12_fp_binop_s_int<0x5D, "min", int_x86_sse_min_ss,
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int_x86_sse2_min_sd, SSE_ALU_ITINS_S>;
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basic_sse12_fp_binop_s_int<0x5D, "min", X86fmins, SSE_ALU_ITINS_S>;
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}
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let isCodeGenOnly = 1 in {
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@ -811,18 +811,18 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::FMAX_RND),
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X86_INTRINSIC_DATA(avx512_mask_max_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMAX,
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X86ISD::FMAX_RND),
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X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FMAX_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FMAX_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK,
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X86ISD::FMAXS, X86ISD::FMAX_RND),
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X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK,
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X86ISD::FMAXS, X86ISD::FMAX_RND),
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X86_INTRINSIC_DATA(avx512_mask_min_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
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X86ISD::FMIN_RND),
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X86_INTRINSIC_DATA(avx512_mask_min_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
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X86ISD::FMIN_RND),
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X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FMIN_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FMIN_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK,
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X86ISD::FMINS, X86ISD::FMIN_RND),
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X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK,
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X86ISD::FMINS, X86ISD::FMIN_RND),
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X86_INTRINSIC_DATA(avx512_mask_mul_pd_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
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X86ISD::FMUL_RND),
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X86_INTRINSIC_DATA(avx512_mask_mul_ps_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
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@ -1604,7 +1604,9 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
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X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
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X86_INTRINSIC_DATA(sse_max_ps, INTR_TYPE_2OP, X86ISD::FMAX, 0),
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X86_INTRINSIC_DATA(sse_max_ss, INTR_TYPE_2OP, X86ISD::FMAXS, 0),
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X86_INTRINSIC_DATA(sse_min_ps, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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X86_INTRINSIC_DATA(sse_min_ss, INTR_TYPE_2OP, X86ISD::FMINS, 0),
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X86_INTRINSIC_DATA(sse_movmsk_ps, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(sse_rcp_ps, INTR_TYPE_1OP, X86ISD::FRCP, 0),
|
||||
X86_INTRINSIC_DATA(sse_rsqrt_ps, INTR_TYPE_1OP, X86ISD::FRSQRT, 0),
|
||||
@ -1627,7 +1629,9 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86_INTRINSIC_DATA(sse2_cvttpd2dq, INTR_TYPE_1OP, X86ISD::CVTTP2SI, 0),
|
||||
X86_INTRINSIC_DATA(sse2_cvttps2dq, INTR_TYPE_1OP, ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(sse2_max_pd, INTR_TYPE_2OP, X86ISD::FMAX, 0),
|
||||
X86_INTRINSIC_DATA(sse2_max_sd, INTR_TYPE_2OP, X86ISD::FMAXS, 0),
|
||||
X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
|
||||
X86_INTRINSIC_DATA(sse2_min_sd, INTR_TYPE_2OP, X86ISD::FMINS, 0),
|
||||
X86_INTRINSIC_DATA(sse2_movmsk_pd, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
|
||||
X86_INTRINSIC_DATA(sse2_packssdw_128, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
|
||||
X86_INTRINSIC_DATA(sse2_packsswb_128, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
|
||||
|
||||
@ -322,10 +322,15 @@ define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; SSE-NEXT: maxss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x5f,0xc1]
|
||||
; SSE-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; VCHECK-LABEL: test_x86_sse_max_ss:
|
||||
; VCHECK: ## BB#0:
|
||||
; VCHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5f,0xc1]
|
||||
; VCHECK-NEXT: retl ## encoding: [0xc3]
|
||||
; AVX2-LABEL: test_x86_sse_max_ss:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5f,0xc1]
|
||||
; AVX2-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; SKX-LABEL: test_x86_sse_max_ss:
|
||||
; SKX: ## BB#0:
|
||||
; SKX-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5f,0xc1]
|
||||
; SKX-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
@ -359,10 +364,15 @@ define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; SSE-NEXT: minss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x5d,0xc1]
|
||||
; SSE-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; VCHECK-LABEL: test_x86_sse_min_ss:
|
||||
; VCHECK: ## BB#0:
|
||||
; VCHECK-NEXT: vminss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5d,0xc1]
|
||||
; VCHECK-NEXT: retl ## encoding: [0xc3]
|
||||
; AVX2-LABEL: test_x86_sse_min_ss:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vminss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5d,0xc1]
|
||||
; AVX2-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; SKX-LABEL: test_x86_sse_min_ss:
|
||||
; SKX: ## BB#0:
|
||||
; SKX-NEXT: vminss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5d,0xc1]
|
||||
; SKX-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
@ -587,10 +587,15 @@ define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) {
|
||||
; SSE-NEXT: maxsd %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x5f,0xc1]
|
||||
; SSE-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; VCHECK-LABEL: test_x86_sse2_max_sd:
|
||||
; VCHECK: ## BB#0:
|
||||
; VCHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5f,0xc1]
|
||||
; VCHECK-NEXT: retl ## encoding: [0xc3]
|
||||
; AVX2-LABEL: test_x86_sse2_max_sd:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5f,0xc1]
|
||||
; AVX2-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; SKX-LABEL: test_x86_sse2_max_sd:
|
||||
; SKX: ## BB#0:
|
||||
; SKX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5f,0xc1]
|
||||
; SKX-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
@ -624,10 +629,15 @@ define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) {
|
||||
; SSE-NEXT: minsd %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x5d,0xc1]
|
||||
; SSE-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; VCHECK-LABEL: test_x86_sse2_min_sd:
|
||||
; VCHECK: ## BB#0:
|
||||
; VCHECK-NEXT: vminsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5d,0xc1]
|
||||
; VCHECK-NEXT: retl ## encoding: [0xc3]
|
||||
; AVX2-LABEL: test_x86_sse2_min_sd:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vminsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5d,0xc1]
|
||||
; AVX2-NEXT: retl ## encoding: [0xc3]
|
||||
;
|
||||
; SKX-LABEL: test_x86_sse2_min_sd:
|
||||
; SKX: ## BB#0:
|
||||
; SKX-NEXT: vminsd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5d,0xc1]
|
||||
; SKX-NEXT: retl ## encoding: [0xc3]
|
||||
%res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user