From 5943ec6923d64e63b9645aa230cd9b86bd63a51b Mon Sep 17 00:00:00 2001
From: Rot127 <unisono@quyllur.org>
Date: Tue, 4 Jun 2024 03:29:20 -0500
Subject: [PATCH] Add Alpha and LoongArch to the CI tests.

---
 compare_tblgen_output.sh       | 2 +-
 gen_cs_tables.sh               | 4 ++--
 gen_llvm_tables.sh             | 4 ++--
 llvm/lib/Target/Alpha/Alpha.td | 3 ---
 4 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/compare_tblgen_output.sh b/compare_tblgen_output.sh
index 5b36f224a48b..d38d7865e64d 100755
--- a/compare_tblgen_output.sh
+++ b/compare_tblgen_output.sh
@@ -1,7 +1,7 @@
 #!/bin/sh
 
 # Compare the generated tables of our refactored TableGen to the original ones.
-archs="AArch64 ARM PPC"
+archs="AArch64 ARM PPC LoongArch"
 file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
 release="18"
 repo_root=$(git rev-parse --show-toplevel)
diff --git a/gen_cs_tables.sh b/gen_cs_tables.sh
index 1fed27b93321..9dd11c128055 100755
--- a/gen_cs_tables.sh
+++ b/gen_cs_tables.sh
@@ -3,7 +3,7 @@
 # Compare the generated tables of our refactored TableGen to the original ones.
 
 # We skip Alpha because it is no longer supported by upstream LLVM
-archs="AArch64 ARM PPC"
+archs="AArch64 ARM PPC LoongArch Alpha"
 file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
 release="18"
 repo_root=$(git rev-parse --show-toplevel)
@@ -48,7 +48,7 @@ gen_all()
       elif [ $file_name = "GenSubtargetInfo" ]; then
         $repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
       elif [ $file_name = "GenSystemOperands" ]; then
-        if [ $arch != "PPC" ] ; then
+        if [ $arch != "PPC" ] && [ $arch != "LoongArch" ] ; then
           $repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
         fi
       else
diff --git a/gen_llvm_tables.sh b/gen_llvm_tables.sh
index c5014027b37e..a3e07e9b058c 100755
--- a/gen_llvm_tables.sh
+++ b/gen_llvm_tables.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-archs="AArch64 ARM PPC"
+archs="AArch64 ARM PPC LoongArch Alpha"
 file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
 release="18"
 repo_root=$(git rev-parse --show-toplevel)
@@ -45,7 +45,7 @@ gen_all()
       elif [ $file_name = "GenSubtargetInfo" ]; then
         $repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
       elif [ $file_name = "GenSystemOperands" ]; then
-        if [ $arch != "PPC" ] ; then
+        if [ $arch != "PPC" ] && [ $arch != "LoongArch" ] ; then
           $repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
         fi
       else
diff --git a/llvm/lib/Target/Alpha/Alpha.td b/llvm/lib/Target/Alpha/Alpha.td
index 38a5b9c186ba..9733d99a0e2b 100644
--- a/llvm/lib/Target/Alpha/Alpha.td
+++ b/llvm/lib/Target/Alpha/Alpha.td
@@ -48,9 +48,6 @@ include "AlphaSchedule.td"
 include "AlphaInstrInfo.td"
 
 def AlphaInstrInfo : InstrInfo {
-  let noNamedPositionallyEncodedOperands = 1;
-  let useDeprecatedPositionallyEncodedOperands = 1;
-  let decodePositionallyEncodedOperands = 1;
 }
 
 //===----------------------------------------------------------------------===//