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[AMDGPU,BPF,SystemZ,WebAssembly] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

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This commit is contained in:
Fangrui Song 2023-06-09 12:26:19 -07:00
parent 8006c7e3f2
commit 5c1fd7b89b
5 changed files with 42 additions and 39 deletions
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32
llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
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@ -39,7 +39,7 @@ public:
R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;
/// Encode the instruction and write it to the OS.
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
@ -49,9 +49,8 @@ public:
const MCSubtargetInfo &STI) const;
private:
void Emit(uint32_t value, raw_ostream &OS) const;
void Emit(uint64_t value, raw_ostream &OS) const;
void emit(uint32_t value, SmallVectorImpl<char> &CB) const;
void emit(uint64_t value, SmallVectorImpl<char> &CB) const;
unsigned getHWReg(unsigned regNo) const;
@ -84,7 +83,8 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo());
}
void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
void R600MCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
@ -101,9 +101,9 @@ void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
InstWord2 |= 1 << 19; // Mega-Fetch bit
}
Emit(InstWord01, OS);
Emit(InstWord2, OS);
Emit((uint32_t) 0, OS);
emit(InstWord01, CB);
emit(InstWord2, CB);
emit((uint32_t)0, CB);
} else if (IS_TEX(Desc)) {
int64_t Sampler = MI.getOperand(14).getImm();
@ -125,9 +125,9 @@ void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
Offsets[2] << 10;
Emit(Word01, OS);
Emit(Word2, OS);
Emit((uint32_t) 0, OS);
emit(Word01, CB);
emit(Word2, CB);
emit((uint32_t)0, CB);
} else {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
if ((STI.hasFeature(R600::FeatureR600ALUInst)) &&
@ -137,16 +137,16 @@ void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
Inst &= ~(0x3FFULL << 39);
Inst |= ISAOpCode << 1;
}
Emit(Inst, OS);
emit(Inst, CB);
}
}
void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
support::endian::write(OS, Value, support::little);
void R600MCCodeEmitter::emit(uint32_t Value, SmallVectorImpl<char> &CB) const {
support::endian::write(CB, Value, support::little);
}
void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
support::endian::write(OS, Value, support::little);
void R600MCCodeEmitter::emit(uint64_t Value, SmallVectorImpl<char> &CB) const {
support::endian::write(CB, Value, support::little);
}
unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {

17
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -26,6 +26,7 @@
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/EndianStream.h"
#include <optional>
using namespace llvm;
@ -47,7 +48,7 @@ public:
SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
/// Encode the instruction and write it to the OS.
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
@ -316,7 +317,8 @@ static bool isVCMPX64(const MCInstrDesc &Desc) {
Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);
}
void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
void SIMCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
int Opcode = MI.getOpcode();
@ -345,7 +347,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
for (unsigned i = 0; i < bytes; i++) {
OS.write((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i));
CB.push_back((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i));
}
// NSA encoding.
@ -361,10 +363,9 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
for (unsigned i = 0; i < NumExtraAddrs; ++i) {
getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), Encoding, Fixups,
STI);
OS.write((uint8_t)Encoding.getLimitedValue());
CB.push_back((uint8_t)Encoding.getLimitedValue());
}
for (unsigned i = 0; i < NumPadding; ++i)
OS.write(0);
CB.append(NumPadding, 0);
}
if ((bytes > 8 && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) ||
@ -400,9 +401,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
} else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
llvm_unreachable("Must be immediate or expr");
for (unsigned j = 0; j < 4; j++) {
OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
}
support::endian::write<uint32_t>(CB, Imm, support::endianness::little);
// Only one literal value allowed
break;

18
llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
View File

@ -58,7 +58,7 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
};
@ -107,20 +107,22 @@ static uint8_t SwapBits(uint8_t Val)
return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
}
void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Opcode = MI.getOpcode();
raw_svector_ostream OS(CB);
support::endian::Writer OSE(OS,
IsLittleEndian ? support::little : support::big);
if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
OS << char(Value >> 56);
CB.push_back(Value >> 56);
if (IsLittleEndian)
OS << char((Value >> 48) & 0xff);
CB.push_back((Value >> 48) & 0xff);
else
OS << char(SwapBits((Value >> 48) & 0xff));
CB.push_back(SwapBits((Value >> 48) & 0xff));
OSE.write<uint16_t>(0);
OSE.write<uint32_t>(Value & 0xffffFFFF);
@ -133,11 +135,11 @@ void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
} else {
// Get instruction encoding and emit it
uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
OS << char(Value >> 56);
CB.push_back(Value >> 56);
if (IsLittleEndian)
OS << char((Value >> 48) & 0xff);
CB.push_back(char((Value >> 48) & 0xff));
else
OS << char(SwapBits((Value >> 48) & 0xff));
CB.push_back(SwapBits((Value >> 48) & 0xff));
OSE.write<uint16_t>((Value >> 32) & 0xffff);
OSE.write<uint32_t>(Value & 0xffffFFFF);
}

7
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -47,7 +47,7 @@ public:
~SystemZMCCodeEmitter() override = default;
// OVerride MCCodeEmitter.
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
@ -154,7 +154,8 @@ private:
} // end anonymous namespace
void SystemZMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
void SystemZMCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MemOpsEmitted = 0;
@ -163,7 +164,7 @@ void SystemZMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
// Big-endian insertion of Size bytes.
unsigned ShiftValue = (Size * 8) - 8;
for (unsigned I = 0; I != Size; ++I) {
OS << uint8_t(Bits >> ShiftValue);
CB.push_back(uint8_t(Bits >> ShiftValue));
ShiftValue -= 8;
}
}

7
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
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@ -43,7 +43,7 @@ class WebAssemblyMCCodeEmitter final : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
@ -57,8 +57,9 @@ MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) {
}
void WebAssemblyMCCodeEmitter::encodeInstruction(
const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
raw_svector_ostream OS(CB);
uint64_t Start = OS.tell();
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);