Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-11-24 06:10:12 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

[UpdateTestChecks] Default --x86_scrub_rip to False

Browse Source 
True is a bad default: the useful symbol names and `@GOTPCREL` are scrubbed.

Change the default and add global variable tests to x86-basic.ll
(renamed from x86_function_name.ll since we now also test variables).
I updated some tests to show the differences.

Updated LCPI regex to include Darwin style `LCPI_[0-9]+_[0-9]+` (no
leading dot).

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D102588
This commit is contained in:
Fangrui Song 2021-05-21 19:26:15 -07:00
parent e162dc6f28
commit 5d9ea36baf
16 changed files with 1106 additions and 1025 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
View File

@ -14,16 +14,16 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movq {{.*}}(%rip), %r8
; CHECK-NEXT: movq {{.*}}(%rip), %r10
; CHECK-NEXT: movq {{.*}}(%rip), %r9
; CHECK-NEXT: movq {{.*}}(%rip), %r12
; CHECK-NEXT: movq {{.*}}(%rip), %r15
; CHECK-NEXT: movq {{.*}}(%rip), %r14
; CHECK-NEXT: movq {{.*}}(%rip), %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: movq X(%rip), %r8
; CHECK-NEXT: movq X(%rip), %r10
; CHECK-NEXT: movq X(%rip), %r9
; CHECK-NEXT: movq X(%rip), %r12
; CHECK-NEXT: movq X(%rip), %r15
; CHECK-NEXT: movq X(%rip), %r14
; CHECK-NEXT: movq X(%rip), %r11
; CHECK-NEXT: movq X(%rip), %rdx
; CHECK-NEXT: addq %r15, %rdx
; CHECK-NEXT: movq {{.*}}(%rip), %rsi
; CHECK-NEXT: movq X(%rip), %rsi
; CHECK-NEXT: bswapq %rsi
; CHECK-NEXT: leaq (%r11,%r14), %rbx
; CHECK-NEXT: addq %r15, %rbx
@ -32,7 +32,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r9,%r10), %rsi
; CHECK-NEXT: leaq (%rsi,%r8), %rdx
; CHECK-NEXT: addq %rsi, %rdx
; CHECK-NEXT: movq {{.*}}(%rip), %rdi
; CHECK-NEXT: movq X(%rip), %rdi
; CHECK-NEXT: addq %rbx, %r12
; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: bswapq %rdi
@ -44,7 +44,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r10,%r8), %rbx
; CHECK-NEXT: leaq (%rdx,%rbx), %rsi
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r12, %rdi
; CHECK-NEXT: addq %rdi, %r9
; CHECK-NEXT: addq %rdx, %rsi
@ -57,7 +57,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%rdx,%r8), %rax
; CHECK-NEXT: leaq (%rsi,%rax), %rdi
; CHECK-NEXT: addq %rax, %rdi
; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: movq X(%rip), %rcx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rsi, %rdi
@ -70,7 +70,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: leaq (%rdi,%rbx), %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r10, %rcx
; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %rdi, %r11
@ -83,7 +83,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: leaq (%r11,%rax), %r14
; CHECK-NEXT: addq %rax, %r14
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: addq %r11, %r14
@ -96,7 +96,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r11,%rdi), %rbx
; CHECK-NEXT: leaq (%r14,%rbx), %r9
; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: addq %r14, %r9
@ -109,7 +109,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r14,%r11), %rax
; CHECK-NEXT: leaq (%r9,%rax), %r10
; CHECK-NEXT: addq %rax, %r10
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: addq %r9, %r10
@ -122,7 +122,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r9,%r14), %rbx
; CHECK-NEXT: leaq (%r10,%rbx), %r8
; CHECK-NEXT: addq %rbx, %r8
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: addq %rax, %r11
; CHECK-NEXT: addq %r10, %r8
@ -135,7 +135,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r10,%r9), %rax
; CHECK-NEXT: leaq (%r8,%rax), %r15
; CHECK-NEXT: addq %rax, %r15
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: addq %rbx, %r14
; CHECK-NEXT: addq %r8, %r15
@ -148,7 +148,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: leaq (%r15,%rbx), %rsi
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r14, %rax
; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: addq %r15, %rsi
@ -161,7 +161,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r15,%r8), %rax
; CHECK-NEXT: leaq (%rsi,%rax), %r12
; CHECK-NEXT: addq %rax, %r12
; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: movq X(%rip), %rcx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rsi, %r12
@ -174,7 +174,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%rsi,%r15), %rbx
; CHECK-NEXT: leaq (%r12,%rbx), %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: movq X(%rip), %rbx
; CHECK-NEXT: addq %r10, %rcx
; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %r12, %rax
@ -187,7 +187,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: leaq (%r12,%rsi), %rdx
; CHECK-NEXT: leaq (%rax,%rdx), %rcx
; CHECK-NEXT: addq %rdx, %rcx
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: movq X(%rip), %rdx
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rbx, %r15
; CHECK-NEXT: addq %rax, %rcx
@ -204,7 +204,7 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: movq X(%rip), %rdx
; CHECK-NEXT: bswapq %rdx
; CHECK-NEXT: addq %r10, %rdx
; CHECK-NEXT: leaq (%r15,%r8), %rdi
@ -218,9 +218,9 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: addq %rdx, %r12
; CHECK-NEXT: addq %rdx, %rdi
; CHECK-NEXT: addq %r15, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: movq X(%rip), %rax
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movq %rax, X(%rip)
; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %r12, %rsi
; CHECK-NEXT: addq %rsi, %rax

4
llvm/test/CodeGen/X86/WidenArith.ll
View File

@ -11,7 +11,7 @@ define <8 x i32> @test(<8 x float> %a, <8 x float> %b) {
; X86-NEXT: vcmpltps %ymm1, %ymm0, %ymm0
; X86-NEXT: vcmpltps %ymm3, %ymm2, %ymm1
; X86-NEXT: vandps %ymm1, %ymm0, %ymm0
; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: test:
@ -22,7 +22,7 @@ define <8 x i32> @test(<8 x float> %a, <8 x float> %b) {
; X64-NEXT: vcmpltps %ymm1, %ymm0, %ymm0
; X64-NEXT: vcmpltps %ymm3, %ymm2, %ymm1
; X64-NEXT: vandps %ymm1, %ymm0, %ymm0
; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
%c1 = fadd <8 x float> %a, %b
%b1 = fmul <8 x float> %b, %a

1964
llvm/test/CodeGen/X86/abi-isel.ll
View File

File diff suppressed because it is too large Load Diff

6
llvm/test/CodeGen/X86/xor.ll
View File

@ -373,18 +373,18 @@ define i32 @test9(i32 %a) nounwind {
define <4 x i32> @test10(<4 x i32> %a) nounwind {
; X86-LABEL: test10:
; X86: # %bb.0:
; X86-NEXT: andnps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl
;
; X64-LIN-LABEL: test10:
; X64-LIN: # %bb.0:
; X64-LIN-NEXT: andnps {{.*}}(%rip), %xmm0
; X64-LIN-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test10:
; X64-WIN: # %bb.0:
; X64-WIN-NEXT: movaps (%rcx), %xmm0
; X64-WIN-NEXT: andnps __xmm@{{.*}}(%rip), %xmm0
; X64-WIN-NEXT: andnps __xmm@00001000000010000000100000001000(%rip), %xmm0
; X64-WIN-NEXT: retq
%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>

11
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_function_name.ll → llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86-basic.ll
View File

@ -7,6 +7,9 @@
;; Check that we accept .seh_proc below the function label.
; RUN: llc -mtriple=x86_64-windows -relocation-model=pic < %s | FileCheck %s --check-prefix=WIN
@gv0 = dso_local global i32 0, align 4
@gv1 = dso_preemptable global i32 0, align 4
define hidden i32 @"_Z54bar$ompvariant$bar"() {
entry:
ret i32 2
@ -19,3 +22,11 @@ entry:
}
declare void @ext()
define i32 @load() {
entry:
%a = load i32, i32* @gv0
%b = load i32, i32* @gv1
%c = add i32 %a, %b
ret i32 %c
}

30
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_function_name.ll.expected → llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86-basic.ll.expected
View File

@ -8,6 +8,9 @@
;; Check that we accept .seh_proc below the function label.
; RUN: llc -mtriple=x86_64-windows -relocation-model=pic < %s | FileCheck %s --check-prefix=WIN
@gv0 = dso_local global i32 0, align 4
@gv1 = dso_preemptable global i32 0, align 4
define hidden i32 @"_Z54bar$ompvariant$bar"() {
; CHECK-LABEL: _Z54bar$ompvariant$bar:
; CHECK: # %bb.0: # %entry
@ -64,3 +67,30 @@ entry:
}
declare void @ext()
define i32 @load() {
; CHECK-LABEL: load:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl gv0(%rip), %eax
; CHECK-NEXT: movq gv1@GOTPCREL(%rip), %rcx
; CHECK-NEXT: addl (%rcx), %eax
; CHECK-NEXT: retq
;
; PIC-LABEL: load:
; PIC: # %bb.0: # %entry
; PIC-NEXT: movl .Lgv0$local(%rip), %eax
; PIC-NEXT: movq gv1@GOTPCREL(%rip), %rcx
; PIC-NEXT: addl (%rcx), %eax
; PIC-NEXT: retq
;
; WIN-LABEL: load:
; WIN: # %bb.0: # %entry
; WIN-NEXT: movl gv0(%rip), %eax
; WIN-NEXT: addl gv1(%rip), %eax
; WIN-NEXT: retq
entry:
%a = load i32, i32* @gv0
%b = load i32, i32* @gv1
%c = add i32 %a, %b
ret i32 %c
}

18
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86-constant-pool.ll Normal file
View File

@ -0,0 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse4.2 | FileCheck %s --check-prefixes=ELF
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.2 | FileCheck %s --check-prefixes=DARWIN
define <4 x i32> @test(<4 x i32> %a) nounwind {
; ELF-LABEL: test10:
; ELF: # %bb.0:
; ELF-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ELF-NEXT: retq
;
; DARWIN-LABEL: test10:
; DARWIN: ## %bb.0:
; DARWIN-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; DARWIN-NEXT: retq
%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
ret <4 x i32> %2
}

18
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86-constant-pool.ll.expected Normal file
View File

@ -0,0 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse4.2 | FileCheck %s --check-prefixes=ELF
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.2 | FileCheck %s --check-prefixes=DARWIN
define <4 x i32> @test(<4 x i32> %a) nounwind {
; ELF-LABEL: test:
; ELF: # %bb.0:
; ELF-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ELF-NEXT: retq
;
; DARWIN-LABEL: test:
; DARWIN: ## %bb.0:
; DARWIN-NEXT: andnps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; DARWIN-NEXT: retq
%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
ret <4 x i32> %2
}

2
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected
View File

@ -105,7 +105,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: subq $20, %rsp
; CHECK-NEXT: movl $0, -20(%rbp)
; CHECK-NEXT: callq OUTLINED_FUNCTION_1
; CHECK-NEXT: movl $1, {{.*}}(%rip)
; CHECK-NEXT: movl $1, x(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: callq OUTLINED_FUNCTION_1

2
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected
View File

@ -82,7 +82,7 @@ define dso_local i32 @main() #0 {
; CHECK-NEXT: subq $20, %rsp
; CHECK-NEXT: movl $0, -20(%rbp)
; CHECK-NEXT: callq OUTLINED_FUNCTION_1
; CHECK-NEXT: movl $1, {{.*}}(%rip)
; CHECK-NEXT: movl $1, x(%rip)
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: callq OUTLINED_FUNCTION_1

6
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/basic.test
View File

@ -12,14 +12,14 @@
# RUN: echo '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub' > %t.expected.ll
# RUN: cat %S/Inputs/basic.ll.expected >> %t.expected.ll
# RUN: diff -u %t.expected.ll %t.ll
# RUN: cp -f %S/Inputs/basic.ll %t.ll && %update_llc_test_checks --no_x86_scrub_rip %t.ll
# RUN: echo '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip' > %t.expected.ll
# RUN: cp -f %S/Inputs/basic.ll %t.ll && %update_llc_test_checks --x86_scrub_rip %t.ll
# RUN: echo '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --x86_scrub_rip' > %t.expected.ll
# RUN: cat %S/Inputs/basic.ll.expected >> %t.expected.ll
# RUN: diff -u %t.expected.ll %t.ll
## Finally, run the script on an already updated file and verify that all previous
## CHECK lines are removed.
# RUN: %update_llc_test_checks %t.ll
# RUN: echo '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip' > %t.expected.ll
# RUN: echo '; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --x86_scrub_rip' > %t.expected.ll
# RUN: cat %S/Inputs/basic.ll.expected >> %t.expected.ll
# RUN: diff -u %t.expected.ll %t.ll

5
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-basic.test Normal file
View File

@ -0,0 +1,5 @@
# REQUIRES: x86-registered-target
## Check that functions names with '$' are processed correctly
# RUN: cp -f %S/Inputs/x86-basic.ll %t.ll && %update_llc_test_checks %t.ll
# RUN: diff -u %S/Inputs/x86-basic.ll.expected %t.ll

4
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-constant-pool.test Normal file
View File

@ -0,0 +1,4 @@
# REQUIRES: x86-registered-target
# RUN: cp -f %S/Inputs/x86-constant-pool.ll %t.ll && %update_llc_test_checks %t.ll
# RUN: diff -u %S/Inputs/x86-constant-pool.ll.expected %t.ll

5
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/x86-function-name.test
View File

@ -1,5 +0,0 @@
# REQUIRES: x86-registered-target
## Check that functions names with '$' are processed correctly
# RUN: cp -f %S/Inputs/x86_function_name.ll %t.ll && %update_llc_test_checks %t.ll
# RUN: diff -u %S/Inputs/x86_function_name.ll.expected %t.ll

4
llvm/utils/UpdateTestChecks/asm.py
View File

@ -171,7 +171,7 @@ SCRUB_X86_SPILL_RELOAD_RE = (
flags=re.M))
SCRUB_X86_SP_RE = re.compile(r'\d+\(%(esp|rsp)\)')
SCRUB_X86_RIP_RE = re.compile(r'[.\w]+\(%rip\)')
SCRUB_X86_LCP_RE = re.compile(r'\.LCPI[0-9]+_[0-9]+')
SCRUB_X86_LCP_RE = re.compile(r'\.?LCPI[0-9]+_[0-9]+')
SCRUB_X86_RET_RE = re.compile(r'ret[l|q]')
def scrub_asm_x86(asm, args):
@ -197,7 +197,7 @@ def scrub_asm_x86(asm, args):
# Generically match a RIP-relative memory operand.
asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm)
# Generically match a LCP symbol.
asm = SCRUB_X86_LCP_RE.sub(r'{{\.LCPI[0-9]+_[0-9]+}}', asm)
asm = SCRUB_X86_LCP_RE.sub(r'{{\.?LCPI[0-9]+_[0-9]+}}', asm)
if getattr(args, 'extra_scrub', False):
# Avoid generating different checks for 32- and 64-bit because of 'retl' vs 'retq'.
asm = SCRUB_X86_RET_RE.sub(r'ret{{[l|q]}}', asm)

2
llvm/utils/update_llc_test_checks.py
View File

@ -33,7 +33,7 @@ def main():
parser.add_argument(
'--no_x86_scrub_sp', action='store_false', dest='x86_scrub_sp')
parser.add_argument(
'--x86_scrub_rip', action='store_true', default=True,
'--x86_scrub_rip', action='store_true', default=False,
help='Use more regex for x86 rip matching to reduce diffs between various subtargets')
parser.add_argument(
'--no_x86_scrub_rip', action='store_false', dest='x86_scrub_rip')