Fix: Src operand is not the out operand

2024-11-23 05:40:09 +00:00 · 2024-09-07 09:46:42 -05:00 · 2024-09-07 09:46:42 -05:00 · 600a1b3d97
commit 600a1b3d97
parent 139e42930c
1 changed files with 1 additions and 1 deletions
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@ -11785,7 +11785,7 @@ class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
 class BaseCAS<string order, string size, RegisterClass RC>
      : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
                        "cas" # order # size, "\t$Rs, $Rt, [$Rn]",
-                        "$out = $Rs",[]>,
+                        "$out = $Rn",[]>,
        Sched<[WriteAtomic]> {
  let NP = 1;
 }