From 600a1b3d9758ab8bfa4934c96c958f426a51fac5 Mon Sep 17 00:00:00 2001
From: Rot127 <unisono@quyllur.org>
Date: Sat, 7 Sep 2024 09:46:42 -0500
Subject: [PATCH] Fix: Src operand is not the out operand

---
 llvm/lib/Target/AArch64/AArch64InstrFormats.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index d9fc9e246218..59020f3af614 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -11785,7 +11785,7 @@ class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
 class BaseCAS<string order, string size, RegisterClass RC>
       : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
                         "cas" # order # size, "\t$Rs, $Rt, [$Rn]",
-                        "$out = $Rs",[]>,
+                        "$out = $Rn",[]>,
         Sched<[WriteAtomic]> {
   let NP = 1;
 }