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[AMDGPU] Use inreg for hint to preload kernel arguments
This patch is the first in a series that adds support for pre-loading kernel arguments into SGPRs. The command-line argument 'amdgpu-kernarg-preload-count' is used to specify the number of arguments sequentially from the first that we should attempt to preload, the default is 0. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D156852
This commit is contained in:
Austin Kerbow
parent
a50486fd73
commit
60a227c464
@ -28,6 +28,10 @@ void initializeCycleInfoWrapperPassPass(PassRegistry &);
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using namespace llvm;
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static cl::opt<unsigned> KernargPreloadCount(
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"amdgpu-kernarg-preload-count",
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cl::desc("How many kernel arguments to preload onto SGPRs"), cl::init(0));
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#define AMDGPU_ATTRIBUTE(Name, Str) Name##_POS,
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enum ImplicitArgumentPositions {
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@ -914,6 +918,21 @@ AAAMDWavesPerEU &AAAMDWavesPerEU::createForPosition(const IRPosition &IRP,
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llvm_unreachable("AAAMDWavesPerEU is only valid for function position");
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}
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static void addPreloadKernArgHint(Function &F, TargetMachine &TM) {
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const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
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for (unsigned I = 0;
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I < F.arg_size() &&
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I < std::min(KernargPreloadCount.getValue(), ST.getMaxNumUserSGPRs());
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++I) {
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Argument &Arg = *F.getArg(I);
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// Check for incompatible attributes.
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if (Arg.hasByRefAttr() || Arg.hasNestAttr())
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break;
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Arg.addAttr(Attribute::InReg);
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}
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}
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class AMDGPUAttributor : public ModulePass {
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public:
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AMDGPUAttributor() : ModulePass(ID) {}
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@ -960,9 +979,12 @@ public:
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if (!F.isIntrinsic()) {
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A.getOrCreateAAFor<AAAMDAttributes>(IRPosition::function(F));
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A.getOrCreateAAFor<AAUniformWorkGroupSize>(IRPosition::function(F));
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if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
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CallingConv::ID CC = F.getCallingConv();
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if (!AMDGPU::isEntryFunctionCC(CC)) {
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A.getOrCreateAAFor<AAAMDFlatWorkGroupSize>(IRPosition::function(F));
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A.getOrCreateAAFor<AAAMDWavesPerEU>(IRPosition::function(F));
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} else if (CC == CallingConv::AMDGPU_KERNEL) {
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addPreloadKernArgHint(F, *TM);
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}
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}
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}
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263
llvm/test/CodeGen/AMDGPU/preload-kernargs-inreg-hints.ll
Normal file
263
llvm/test/CodeGen/AMDGPU/preload-kernargs-inreg-hints.ll
Normal file
@ -0,0 +1,263 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-attributor -S < %s | FileCheck -check-prefix=NO-PRELOAD %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=1 -amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-1 %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=3 -amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-3 %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=16 -amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-16 %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=20 -amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-20 %s
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define amdgpu_kernel void @test_preload_hint_kernel_1(ptr %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; NO-PRELOAD-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-1-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-3-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-16-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-20-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_2(i32 %0, i64 %1) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_4(i32 %0, i64 %1, <2 x float> %2, ptr %3) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_18(i32 %0, i64 %1, <2 x float> %2, ptr %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16, i32 %17) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], i32 [[TMP6:%.*]], i32 [[TMP7:%.*]], i32 [[TMP8:%.*]], i32 [[TMP9:%.*]], i32 [[TMP10:%.*]], i32 [[TMP11:%.*]], i32 [[TMP12:%.*]], i32 [[TMP13:%.*]], i32 [[TMP14:%.*]], i32 [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], i32 [[TMP6:%.*]], i32 [[TMP7:%.*]], i32 [[TMP8:%.*]], i32 [[TMP9:%.*]], i32 [[TMP10:%.*]], i32 [[TMP11:%.*]], i32 [[TMP12:%.*]], i32 [[TMP13:%.*]], i32 [[TMP14:%.*]], i32 [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], i32 [[TMP6:%.*]], i32 [[TMP7:%.*]], i32 [[TMP8:%.*]], i32 [[TMP9:%.*]], i32 [[TMP10:%.*]], i32 [[TMP11:%.*]], i32 [[TMP12:%.*]], i32 [[TMP13:%.*]], i32 [[TMP14:%.*]], i32 [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]], i32 inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], i32 inreg [[TMP6:%.*]], i32 inreg [[TMP7:%.*]], i32 inreg [[TMP8:%.*]], i32 inreg [[TMP9:%.*]], i32 inreg [[TMP10:%.*]], i32 inreg [[TMP11:%.*]], i32 inreg [[TMP12:%.*]], i32 inreg [[TMP13:%.*]], i32 inreg [[TMP14:%.*]], i32 inreg [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]], i32 inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], i32 inreg [[TMP6:%.*]], i32 inreg [[TMP7:%.*]], i32 inreg [[TMP8:%.*]], i32 inreg [[TMP9:%.*]], i32 inreg [[TMP10:%.*]], i32 inreg [[TMP11:%.*]], i32 inreg [[TMP12:%.*]], i32 inreg [[TMP13:%.*]], i32 inreg [[TMP14:%.*]], i32 inreg [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define void @test_preload_hint_non_kernel_2(i32 %0, i64 %1) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-1-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-3-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-16-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-20-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_1_call_func(ptr %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; NO-PRELOAD-SAME: (ptr [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; NO-PRELOAD-NEXT: call void @func(ptr [[TMP0]])
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-1-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-1-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-3-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-3-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-16-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-16-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-20-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-20-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-20-NEXT: ret void
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;
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call void @func(ptr %0)
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_1_call_intrinsic(i16 %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; NO-PRELOAD-SAME: (i16 [[TMP0:%.*]]) #[[ATTR2]] {
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; NO-PRELOAD-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-1-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR2]] {
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; PRELOAD-1-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-3-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR2]] {
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; PRELOAD-3-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-16-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR2]] {
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; PRELOAD-16-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-20-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR2]] {
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; PRELOAD-20-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-20-NEXT: ret void
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;
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call void @llvm.amdgcn.set.prio(i16 %0)
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ret void
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}
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define spir_kernel void @test_preload_hint_kernel_1_spir_cc(ptr %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; NO-PRELOAD-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-1-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-3-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-16-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-20-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_2_preexisting(i32 inreg %0, i64 %1) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; NO-PRELOAD-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
|
||||
; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
|
||||
; PRELOAD-3-NEXT: ret void
|
||||
;
|
||||
; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
|
||||
; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
|
||||
; PRELOAD-16-NEXT: ret void
|
||||
;
|
||||
; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
|
||||
; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
|
||||
; PRELOAD-20-NEXT: ret void
|
||||
;
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_preload_hint_kernel_incompatible_attributes(ptr addrspace(4) byref(i32) %0, ptr nest %1) {
|
||||
; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
|
||||
; NO-PRELOAD-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; NO-PRELOAD-NEXT: ret void
|
||||
;
|
||||
; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
|
||||
; PRELOAD-1-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; PRELOAD-1-NEXT: ret void
|
||||
;
|
||||
; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
|
||||
; PRELOAD-3-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; PRELOAD-3-NEXT: ret void
|
||||
;
|
||||
; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
|
||||
; PRELOAD-16-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; PRELOAD-16-NEXT: ret void
|
||||
;
|
||||
; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
|
||||
; PRELOAD-20-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; PRELOAD-20-NEXT: ret void
|
||||
;
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @func(ptr) #0
|
||||
declare void @llvm.amdgcn.set.prio(i16)
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
Loading…
Reference in New Issue
Block a user