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https://github.com/capstone-engine/llvm-capstone.git
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[GlobalISel] Add G_ASSERT_SEXT
This adds a G_ASSERT_SEXT opcode, similar to G_ASSERT_ZEXT. This instruction
signifies that an operation was already sign extended from a smaller type.
This is useful for functions with sign-extended parameters.
E.g.
```
define void @foo(i16 signext %x) {
...
}
```
This adds verifier, regbankselect, and instruction selection support for
G_ASSERT_SEXT equivalent to G_ASSERT_ZEXT.
Differential Revision: https://reviews.llvm.org/D96890
This commit is contained in:
Jessica Paquette
parent
10993bf072
commit
60aa646441
@ -742,10 +742,10 @@ Optimization Hints
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These instructions do not correspond to any target instructions. They act as
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hints for various combines.
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G_ASSERT_ZEXT
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G_ASSERT_SEXT, G_ASSERT_ZEXT
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^^^^^^^^^^^^^
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Signifies that the contents of a register were previously zero-extended from a
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Signifies that the contents of a register were previously extended from a
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smaller type.
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The smaller type is denoted using an immediate operand. For scalars, this is the
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@ -754,10 +754,12 @@ element type.
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.. code-block:: none
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%x_assert:_(s32) = G_ASSERT_ZEXT %x(s32), 16
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%y_assert:_(<2 x s32>) = G_ASSERT_ZEXT %y(<2 x s32>), 16
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%x_was_zexted:_(s32) = G_ASSERT_ZEXT %x(s32), 16
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%y_was_zexted:_(<2 x s32>) = G_ASSERT_ZEXT %y(<2 x s32>), 16
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G_ASSERT_ZEXT acts like a restricted form of copy.
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%z_was_sexted:_(s32) = G_ASSERT_SEXT %z(s32), 8
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G_ASSERT_SEXT and G_ASSERT_ZEXT act like copies, albeit with some restrictions.
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The source and destination registers must
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@ -816,6 +816,12 @@ public:
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MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
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unsigned Size);
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/// Build and insert \p Res = G_ASSERT_SEXT Op, Size
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
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unsigned Size);
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/// Build and insert `Res = G_LOAD Addr, MMO`.
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///
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/// Loads the value stored at \p Addr. Puts the result in \p Res.
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@ -215,9 +215,10 @@ HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
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/// Instructions which should not exist past instruction selection, but do not
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/// generate code. These instructions only act as optimization hints.
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HANDLE_TARGET_OPCODE(G_ASSERT_SEXT)
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HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT)
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START,
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G_ASSERT_ZEXT)
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G_ASSERT_SEXT)
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END,
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G_ASSERT_ZEXT)
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@ -1349,3 +1349,11 @@ def G_ASSERT_ZEXT : GenericInstruction {
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let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
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let hasSideEffects = false;
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}
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// Asserts that an operation has already been sign-extended from a specific
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// type.
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def G_ASSERT_SEXT : GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
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let hasSideEffects = false;
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}
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@ -240,6 +240,12 @@ MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
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return buildInstr(TargetOpcode::COPY, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildAssertSExt(const DstOp &Res,
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const SrcOp &Op,
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unsigned Size) {
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return buildInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op).addImm(Size);
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}
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MachineInstrBuilder MachineIRBuilder::buildAssertZExt(const DstOp &Res,
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const SrcOp &Op,
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unsigned Size) {
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@ -623,18 +623,18 @@ bool RegBankSelect::applyMapping(
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bool RegBankSelect::assignInstr(MachineInstr &MI) {
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LLVM_DEBUG(dbgs() << "Assign: " << MI);
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if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
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// We'll probably have a G_ASSERT_SEXT or something similar in the future.
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assert(MI.getOpcode() == TargetOpcode::G_ASSERT_ZEXT &&
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"G_ASSERT_ZEXT is the only hint right now!");
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unsigned Opc = MI.getOpcode();
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if (isPreISelGenericOptimizationHint(Opc)) {
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assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||
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Opc == TargetOpcode::G_ASSERT_SEXT) &&
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"Unexpected hint opcode!");
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// The only correct mapping for these is to always use the source register
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// bank.
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const RegisterBank *RB = MRI->getRegBankOrNull(MI.getOperand(1).getReg());
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// We can assume every instruction above this one has a selected register
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// bank.
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assert(RB && "Expected source register to have a register bank?");
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LLVM_DEBUG(
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dbgs() << "... G_ASSERT_ZEXT always uses source's register bank.\n");
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LLVM_DEBUG(dbgs() << "... Hint always uses source's register bank.\n");
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MRI->setRegBank(MI.getOperand(0).getReg(), *RB);
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return true;
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}
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@ -223,6 +223,7 @@ namespace {
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void report(const char *msg, const MachineInstr *MI);
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void report(const char *msg, const MachineOperand *MO, unsigned MONum,
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LLT MOVRegType = LLT{});
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void report(const Twine &Msg, const MachineInstr *MI);
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void report_context(const LiveInterval &LI) const;
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void report_context(const LiveRange &LR, Register VRegUnit,
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@ -500,6 +501,10 @@ void MachineVerifier::report(const char *msg, const MachineOperand *MO,
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errs() << "\n";
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}
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void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
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report(Msg.str().c_str(), MI);
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}
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void MachineVerifier::report_context(SlotIndex Pos) const {
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errs() << "- at: " << Pos << '\n';
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}
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@ -940,10 +945,14 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
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report(ErrorInfo.data(), MI);
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// Verify properties of various specific instruction types
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switch (MI->getOpcode()) {
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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case TargetOpcode::G_ASSERT_SEXT:
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case TargetOpcode::G_ASSERT_ZEXT: {
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std::string OpcName =
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Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
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if (!MI->getOperand(2).isImm()) {
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report("G_ASSERT_ZEXT expects an immediate operand #2", MI);
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report(Twine(OpcName, " expects an immediate operand #2"), MI);
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break;
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}
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@ -952,24 +961,26 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
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LLT SrcTy = MRI->getType(Src);
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int64_t Imm = MI->getOperand(2).getImm();
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if (Imm <= 0) {
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report("G_ASSERT_ZEXT size must be >= 1", MI);
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report(Twine(OpcName, " size must be >= 1"), MI);
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break;
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}
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if (Imm >= SrcTy.getScalarSizeInBits()) {
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report("G_ASSERT_ZEXT size must be less than source bit width", MI);
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report(Twine(OpcName, " size must be less than source bit width"), MI);
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break;
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}
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if (MRI->getRegBankOrNull(Src) != MRI->getRegBankOrNull(Dst)) {
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report("G_ASSERT_ZEXT source and destination register banks must match",
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MI);
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report(
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Twine(OpcName, " source and destination register banks must match"),
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MI);
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break;
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}
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if (MRI->getRegClassOrNull(Src) != MRI->getRegClassOrNull(Dst))
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report("G_ASSERT_ZEXT source and destination register classes must match",
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MI);
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report(
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Twine(OpcName, " source and destination register classes must match"),
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MI);
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break;
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}
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370
llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
Normal file
370
llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
Normal file
@ -0,0 +1,370 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Verify register banks for G_ASSERT_SEXT.
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#
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...
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---
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name: gpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; G_ASSERT_SEXT should end up on a GPR.
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; CHECK-LABEL: name: gpr
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; CHECK: liveins: $w0, $w1
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; CHECK: %copy:gpr(s32) = COPY $w0
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; CHECK: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
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; CHECK: $w1 = COPY %copy_assert_sext(s32)
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; CHECK: RET_ReallyLR implicit $w1
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%copy:_(s32) = COPY $w0
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%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
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$w1 = COPY %copy_assert_sext(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: gpr_vector
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; G_ASSERT_SEXT should end up on a GPR.
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; CHECK-LABEL: name: gpr_vector
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; CHECK: liveins: $x0, $x1
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; CHECK: %copy:gpr(<2 x s32>) = COPY $x0
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; CHECK: %copy_assert_sext:gpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
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; CHECK: $x1 = COPY %copy_assert_sext(<2 x s32>)
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; CHECK: RET_ReallyLR implicit $x1
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%copy:_(<2 x s32>) = COPY $x0
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%copy_assert_sext:_(<2 x s32>) = G_ASSERT_SEXT %copy(<2 x s32>), 16
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$x1 = COPY %copy_assert_sext(<2 x s32>)
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RET_ReallyLR implicit $x1
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...
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---
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name: fpr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; G_ASSERT_SEXT should end up on a FPR.
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; CHECK-LABEL: name: fpr
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; CHECK: liveins: $s0, $s1
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; CHECK: %copy:fpr(s32) = COPY $s0
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; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
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; CHECK: $s1 = COPY %copy_assert_sext(s32)
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; CHECK: RET_ReallyLR implicit $s1
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%copy:_(s32) = COPY $s0
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%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
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$s1 = COPY %copy_assert_sext(s32)
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RET_ReallyLR implicit $s1
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...
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---
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name: fpr_vector
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; G_ASSERT_SEXT should end up on a FPR.
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; CHECK-LABEL: name: fpr_vector
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; CHECK: liveins: $d0, $d1
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; CHECK: %copy:fpr(<2 x s32>) = COPY $d0
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; CHECK: %copy_assert_sext:fpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
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; CHECK: $d1 = COPY %copy_assert_sext(<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d1
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%copy:_(<2 x s32>) = COPY $d0
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%copy_assert_sext:_(<2 x s32>) = G_ASSERT_SEXT %copy(<2 x s32>), 16
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$d1 = COPY %copy_assert_sext(<2 x s32>)
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RET_ReallyLR implicit $d1
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...
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---
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name: in_between_cross_bank_copy
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $w1
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; CHECK-LABEL: name: in_between_cross_bank_copy
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; CHECK: liveins: $s0, $w1
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; CHECK: %copy:fpr(s32) = COPY $s0
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; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
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; CHECK: $w1 = COPY %copy_assert_sext(s32)
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; CHECK: RET_ReallyLR implicit $w1
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%copy:_(s32) = COPY $s0
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%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
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$w1 = COPY %copy_assert_sext(s32)
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RET_ReallyLR implicit $w1
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...
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---
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name: fpr_feeding_store
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $s0, $s1
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; The G_ASSERT_SEXT should end up on a FPR, and there should be no copy
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; between it and the G_STORE.
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; CHECK-LABEL: name: fpr_feeding_store
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; CHECK: liveins: $x0, $s0, $s1
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; CHECK: %ptr:gpr(p0) = COPY $x0
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; CHECK: %copy:fpr(s32) = COPY $s0
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; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
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; CHECK: G_STORE %copy_assert_sext(s32), %ptr(p0) :: (store 4)
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; CHECK: RET_ReallyLR
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%ptr:_(p0) = COPY $x0
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%copy:_(s32) = COPY $s0
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%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
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G_STORE %copy_assert_sext(s32), %ptr(p0) :: (store 4)
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RET_ReallyLR
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...
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---
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name: fpr_feeding_select
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x1, $w0
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; G_ASSERT_SEXT and G_SELECT should both end up on FPRs.
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; CHECK-LABEL: name: fpr_feeding_select
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; CHECK: liveins: $d0, $x1, $w0
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; CHECK: %w0:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %w0(s32)
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; CHECK: %fpr:fpr(s64) = COPY $d0
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; CHECK: %fpr_assert_sext:fpr(s64) = G_ASSERT_SEXT %fpr, 32
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; CHECK: %gpr:gpr(s64) = COPY $x1
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; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
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; CHECK: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_sext, [[COPY]]
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; CHECK: $d0 = COPY %select(s64)
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; CHECK: RET_ReallyLR implicit $d0
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%w0:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %w0(s32)
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%fpr:_(s64) = COPY $d0
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%fpr_assert_sext:_(s64) = G_ASSERT_SEXT %fpr, 32
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%gpr:_(s64) = COPY $x1
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%select:_(s64) = G_SELECT %cond(s1), %fpr_assert_sext, %gpr
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$d0 = COPY %select(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: fpr_feeding_phi
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fpr_feeding_phi
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $s0, $w1
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; CHECK: %copy1:fpr(s32) = COPY $s0
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; CHECK: %copy2:gpr(s32) = COPY $w1
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; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy1, 16
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; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
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; CHECK: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
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; CHECK: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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; CHECK: G_BRCOND %cmp_trunc(s1), %bb.1
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; CHECK: G_BR %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: %bb1_val:gpr(s32) = COPY %copy2(s32)
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: successors: %bb.0(0x80000000)
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; CHECK: %phi:fpr(s32) = G_PHI %copy_assert_sext(s32), %bb.0, %bb1_val(s32), %bb.1
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; CHECK: G_BR %bb.0
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $s0, $w1
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%copy1:_(s32) = COPY $s0
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%copy2:_(s32) = COPY $w1
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; This should produce a FPR.
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%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy1(s32), 16
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%cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
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%cmp_trunc:_(s1) = G_TRUNC %cmp
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G_BRCOND %cmp_trunc, %bb.1
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G_BR %bb.1
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bb.1:
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successors: %bb.2
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%bb1_val:_(s32) = COPY %copy2
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||||
G_BR %bb.2
|
||||
bb.2:
|
||||
successors: %bb.0
|
||||
; This should produce a FPR.
|
||||
%phi:_(s32) = G_PHI %copy_assert_sext, %bb.0, %bb1_val, %bb.1
|
||||
G_BR %bb.0
|
||||
|
||||
...
|
||||
---
|
||||
name: fed_by_fpr_phi
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; CHECK-LABEL: name: fed_by_fpr_phi
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: liveins: $s0, $s1
|
||||
; CHECK: %copy1:fpr(s32) = COPY $s0
|
||||
; CHECK: %copy2:fpr(s32) = COPY $s1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
|
||||
; CHECK: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
; CHECK: G_BRCOND %cmp_trunc(s1), %bb.1
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: %bb1_val:gpr(s32) = COPY %copy2(s32)
|
||||
; CHECK: G_BR %bb.2
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.0(0x80000000)
|
||||
; CHECK: %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
|
||||
; CHECK: %assert_sext:fpr(s32) = G_ASSERT_SEXT %phi, 16
|
||||
; CHECK: G_BR %bb.0
|
||||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
liveins: $s0, $s1
|
||||
%copy1:_(s32) = COPY $s0
|
||||
%copy2:_(s32) = COPY $s1
|
||||
%cmp:_(s32) = G_ICMP intpred(eq), %copy1, %copy2
|
||||
%cmp_trunc:_(s1) = G_TRUNC %cmp
|
||||
G_BRCOND %cmp_trunc, %bb.1
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
%bb1_val:_(s32) = COPY %copy2
|
||||
G_BR %bb.2
|
||||
bb.2:
|
||||
successors: %bb.0
|
||||
; The G_PHI and G_ASSERT_SEXT should both end up on FPRs.
|
||||
%phi:_(s32) = G_PHI %copy1, %bb.0, %bb1_val, %bb.1
|
||||
%assert_sext:_(s32) = G_ASSERT_SEXT %phi(s32), 16
|
||||
G_BR %bb.0
|
||||
|
||||
...
|
||||
---
|
||||
name: different_blocks_gpr
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; CHECK-LABEL: name: different_blocks_gpr
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %copy:gpr(s32) = COPY $w0
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
; CHECK: $w1 = COPY %copy_assert_sext(s32)
|
||||
; CHECK: RET_ReallyLR implicit $w1
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
liveins: $w0, $w1
|
||||
%copy:_(s32) = COPY $w0
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
; The G_ASSERT_SEXT should end up on a GPR.
|
||||
%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
|
||||
$w1 = COPY %copy_assert_sext
|
||||
RET_ReallyLR implicit $w1
|
||||
|
||||
...
|
||||
---
|
||||
name: different_blocks_fpr
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; CHECK-LABEL: name: different_blocks_fpr
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $s0, $s1
|
||||
; CHECK: %copy:fpr(s32) = COPY $s0
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
; CHECK: $s1 = COPY %copy_assert_sext(s32)
|
||||
; CHECK: RET_ReallyLR implicit $s1
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
liveins: $s0, $s1
|
||||
%copy:_(s32) = COPY $s0
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
; The G_ASSERT_SEXT should end up on a FPR.
|
||||
%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
|
||||
$s1 = COPY %copy_assert_sext
|
||||
RET_ReallyLR implicit $s1
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: different_blocks_fpr_backedge
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; CHECK-LABEL: name: different_blocks_fpr_backedge
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $s0, $s1
|
||||
; CHECK: %copy:fpr(s32) = COPY $s0
|
||||
; CHECK: G_BR %bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: %copy_assert_sext1:fpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
; CHECK: G_BR %bb.2
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.0(0x80000000)
|
||||
; CHECK: %copy_assert_sext2:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext1, 16
|
||||
; CHECK: %copy_assert_sext3:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext2, 16
|
||||
; CHECK: G_BR %bb.0
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
liveins: $s0, $s1
|
||||
%copy:_(s32) = COPY $s0
|
||||
G_BR %bb.1
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
; All of the G_ASSERT_SEXTs should end up on FPRs.
|
||||
%copy_assert_sext1:_(s32) = G_ASSERT_SEXT %copy(s32), 16
|
||||
G_BR %bb.2
|
||||
bb.2:
|
||||
successors: %bb.0
|
||||
%copy_assert_sext2:_(s32) = G_ASSERT_SEXT %copy_assert_sext1(s32), 16
|
||||
%copy_assert_sext3:_(s32) = G_ASSERT_SEXT %copy_assert_sext2(s32), 16
|
||||
G_BR %bb.0
|
||||
@ -1,7 +1,7 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
# Check that we remove G_ASSERT_ZEXT during selection.
|
||||
# Check that we remove hints during selection.
|
||||
|
||||
...
|
||||
---
|
||||
@ -86,3 +86,87 @@ body: |
|
||||
%copy_with_rc:gpr32sp(s32) = COPY $w2
|
||||
$w1 = COPY %copy_with_rc(s32)
|
||||
RET_ReallyLR implicit $w1
|
||||
|
||||
...
|
||||
---
|
||||
name: assert_sext_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1
|
||||
|
||||
; CHECK-LABEL: name: assert_sext_gpr
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %copy:gpr32all = COPY $w0
|
||||
; CHECK: $w1 = COPY %copy
|
||||
; CHECK: RET_ReallyLR implicit $w1
|
||||
%copy:gpr(s32) = COPY $w0
|
||||
%copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
$w1 = COPY %copy_assert_sext(s32)
|
||||
RET_ReallyLR implicit $w1
|
||||
|
||||
...
|
||||
---
|
||||
name: assert_sext_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $s0, $s1
|
||||
|
||||
; CHECK-LABEL: name: assert_sext_fpr
|
||||
; CHECK: liveins: $s0, $s1
|
||||
; CHECK: %copy:fpr32 = COPY $s0
|
||||
; CHECK: $s1 = COPY %copy
|
||||
; CHECK: RET_ReallyLR implicit $s1
|
||||
%copy:fpr(s32) = COPY $s0
|
||||
%copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
$s1 = COPY %copy_assert_sext(s32)
|
||||
RET_ReallyLR implicit $s1
|
||||
|
||||
...
|
||||
---
|
||||
name: assert_sext_in_between_cross_bank
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $s0, $w1
|
||||
|
||||
; CHECK-LABEL: name: assert_sext_in_between_cross_bank
|
||||
; CHECK: liveins: $s0, $w1
|
||||
; CHECK: %copy:fpr32 = COPY $s0
|
||||
; CHECK: $w1 = COPY %copy
|
||||
; CHECK: RET_ReallyLR implicit $w1
|
||||
%copy:fpr(s32) = COPY $s0
|
||||
%copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
$w1 = COPY %copy_assert_sext(s32)
|
||||
RET_ReallyLR implicit $w1
|
||||
|
||||
...
|
||||
---
|
||||
name: assert_sext_decided_dst_class
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1, $w2
|
||||
|
||||
; Users of G_ASSERT_SEXT may end up deciding the destination register class.
|
||||
; Make sure that the source register class is constrained.
|
||||
|
||||
; CHECK-LABEL: name: assert_sext_decided_dst_class
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %copy_with_rc:gpr32sp = COPY $w2
|
||||
; CHECK: $w1 = COPY %copy_with_rc
|
||||
; CHECK: RET_ReallyLR implicit $w1
|
||||
%copy:gpr(s32) = COPY $w0
|
||||
%copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
|
||||
%copy_with_rc:gpr32sp(s32) = COPY $w2
|
||||
$w1 = COPY %copy_with_rc(s32)
|
||||
RET_ReallyLR implicit $w1
|
||||
|
||||
42
llvm/test/MachineVerifier/test_g_assert_sext.mir
Normal file
42
llvm/test/MachineVerifier/test_g_assert_sext.mir
Normal file
@ -0,0 +1,42 @@
|
||||
# REQUIRES: aarch64-registered-target
|
||||
# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
|
||||
|
||||
name: test
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $w0
|
||||
%0:_(s64) = COPY $x0
|
||||
%1:_(<4 x s16>) = COPY $x0
|
||||
%2:_(s32) = COPY $w0
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
|
||||
; CHECK: instruction: %assert_sext_1:_(s64) = G_ASSERT_SEXT
|
||||
%assert_sext_1:_(s64) = G_ASSERT_SEXT %0, %0
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT expects an immediate operand #2 ***
|
||||
; CHECK: instruction: %assert_sext_2:_(s64) = G_ASSERT_SEXT
|
||||
%assert_sext_2:_(s64) = G_ASSERT_SEXT %0, i8 8
|
||||
|
||||
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
||||
; CHECK: instruction: %assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT
|
||||
%assert_sext_3:_(<2 x s32>) = G_ASSERT_SEXT %0, 8
|
||||
|
||||
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
||||
; CHECK: instruction: %assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT
|
||||
%assert_sext_4:_(<2 x s32>) = G_ASSERT_SEXT %1, 8
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be >= 1 ***
|
||||
; CHECK: instruction: %assert_sext_5:_(s64) = G_ASSERT_SEXT
|
||||
%assert_sext_5:_(s64) = G_ASSERT_SEXT %0, 0
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT size must be less than source bit width ***
|
||||
; CHECK: instruction: %assert_sext_6:_(s64) = G_ASSERT_SEXT
|
||||
%assert_sext_6:_(s64) = G_ASSERT_SEXT %0, 128
|
||||
|
||||
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
||||
; CHECK: instruction: %assert_sext_7:_(s64) = G_ASSERT_SEXT %2:_, 8
|
||||
%assert_sext_7:_(s64) = G_ASSERT_SEXT %2, 8
|
||||
|
||||
; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
|
||||
; CHECK: instruction: %assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
|
||||
%assert_sext_8:_(s64) = G_ASSERT_SEXT $x0, 8
|
||||
@ -0,0 +1,35 @@
|
||||
# REQUIRES: aarch64-registered-target
|
||||
# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
|
||||
|
||||
name: test
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1
|
||||
%bank:gpr(s32) = COPY $w0
|
||||
%class:gpr32(s32) = COPY $w1
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register banks must match ***
|
||||
; CHECK: instruction: %bank_mismatch:fpr(s32) = G_ASSERT_SEXT %bank:gpr, 16
|
||||
%bank_mismatch:fpr(s32) = G_ASSERT_SEXT %bank, 16
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register classes must match ***
|
||||
; CHECK: instruction: %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_SEXT %class:gpr32, 16
|
||||
%class_mismatch_gpr:gpr32all(s32) = G_ASSERT_SEXT %class, 16
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register classes must match ***
|
||||
; CHECK: instruction: %class_mismatch_fpr:fpr32(s32) = G_ASSERT_SEXT %class:gpr32, 16
|
||||
%class_mismatch_fpr:fpr32(s32) = G_ASSERT_SEXT %class, 16
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register banks must match ***
|
||||
; CHECK: instruction: %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_SEXT %bank:gpr, 16
|
||||
%dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_SEXT %bank, 16
|
||||
|
||||
; CHECK: *** Bad machine code: G_ASSERT_SEXT source and destination register banks must match ***
|
||||
; CHECK: instruction: %dst_has_bank_src_has_class:gpr(s32) = G_ASSERT_SEXT %class:gpr32, 16
|
||||
%dst_has_bank_src_has_class:gpr(s32) = G_ASSERT_SEXT %class, 16
|
||||
|
||||
; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
|
||||
; CHECK: instruction: %implicit_physreg:gpr(s32) = G_ASSERT_SEXT %class:gpr32, 16, implicit-def $w0
|
||||
%implicit_physreg:gpr(s32) = G_ASSERT_SEXT %class, 16, implicit-def $w0
|
||||
Loading…
Reference in New Issue
Block a user