[SCEV] Use NoWrapFlags when expanding a simple mul

Second functional change following on from rL362687. Pass the
NoWrapFlags from the MulExpr to InsertBinop when we're generating a
shl or mul.

Differential Revision: https://reviews.llvm.org/D61934

llvm-svn: 363540
This commit is contained in:
Sam Parker 2019-06-17 10:05:18 +00:00
parent 46f9cbe28d
commit 60d6fb2a63
11 changed files with 22 additions and 22 deletions

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@ -842,9 +842,9 @@ Value *SCEVExpander::visitMulExpr(const SCEVMulExpr *S) {
assert(!Ty->isVectorTy() && "vector types are not SCEVable");
Prod = InsertBinop(Instruction::Shl, Prod,
ConstantInt::get(Ty, RHS->logBase2()),
SCEV::FlagAnyWrap, /*IsSafeToHoist*/ true);
S->getNoWrapFlags(), /*IsSafeToHoist*/ true);
} else {
Prod = InsertBinop(Instruction::Mul, Prod, W, SCEV::FlagAnyWrap,
Prod = InsertBinop(Instruction::Mul, Prod, W, S->getNoWrapFlags(),
/*IsSafeToHoist*/ true);
}
}

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@ -3,7 +3,7 @@
; Make sure that we generate correct runtime checks.
; CHECK: b7.old:
; CHECK: [[LEN:%[0-9]+]] = shl i32 %len, 3
; CHECK: [[LEN:%[0-9]+]] = shl nuw i32 %len, 3
; CHECK: [[SRC:%[0-9]+]] = ptrtoint i8* %src to i32
; CHECK: [[DST:%[0-9]+]] = ptrtoint i8* %dst to i32
; CHECK: [[ULT:%[0-9]+]] = icmp ult i32 [[DST]], [[SRC]]

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@ -282,7 +282,7 @@ for.end: ; preds = %for.body, %entry
;; memcpy.atomic formation (atomic load & store) -- element size 2
define void @test6(i64 %Size) nounwind ssp {
; CHECK-LABEL: @test6(
; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 1
; CHECK: [[Sz:%[0-9]+]] = shl nuw i64 %Size, 1
; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 2 %Dest{{[0-9]*}}, i8* align 2 %Base{{[0-9]*}}, i64 [[Sz]], i32 2)
; CHECK-NOT: store
; CHECK: ret void
@ -308,7 +308,7 @@ for.end: ; preds = %for.body, %entry
;; memcpy.atomic formation (atomic load & store) -- element size 4
define void @test7(i64 %Size) nounwind ssp {
; CHECK-LABEL: @test7(
; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 2
; CHECK: [[Sz:%[0-9]+]] = shl nuw i64 %Size, 2
; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 %Dest{{[0-9]*}}, i8* align 4 %Base{{[0-9]*}}, i64 [[Sz]], i32 4)
; CHECK-NOT: store
; CHECK: ret void
@ -334,7 +334,7 @@ for.end: ; preds = %for.body, %entry
;; memcpy.atomic formation (atomic load & store) -- element size 8
define void @test8(i64 %Size) nounwind ssp {
; CHECK-LABEL: @test8(
; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 3
; CHECK: [[Sz:%[0-9]+]] = shl nuw i64 %Size, 3
; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 8 %Dest{{[0-9]*}}, i8* align 8 %Base{{[0-9]*}}, i64 [[Sz]], i32 8)
; CHECK-NOT: store
; CHECK: ret void
@ -360,7 +360,7 @@ for.end: ; preds = %for.body, %entry
;; memcpy.atomic formation rejection (atomic load & store) -- element size 16
define void @test9(i64 %Size) nounwind ssp {
; CHECK-LABEL: @test9(
; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 4
; CHECK: [[Sz:%[0-9]+]] = shl nuw i64 %Size, 4
; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 16 %Dest{{[0-9]*}}, i8* align 16 %Base{{[0-9]*}}, i64 [[Sz]], i32 16)
; CHECK-NOT: store
; CHECK: ret void

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@ -46,7 +46,7 @@ for.end: ; preds = %for.body, %entry
ret void
; CHECK-LABEL: @test1_i16(
; CHECK: %[[BaseBC:.*]] = bitcast i16* %Base to i8*
; CHECK: %[[Sz:[0-9]+]] = shl i64 %Size, 1
; CHECK: %[[Sz:[0-9]+]] = shl nuw i64 %Size, 1
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 2 %[[BaseBC]], i8 0, i64 %[[Sz]], i1 false)
; CHECK-NOT: store
}
@ -92,7 +92,7 @@ for.end: ; preds = %for.body, %entry
ret void
; CHECK-LABEL: @test2(
; CHECK: br i1 %cmp10,
; CHECK: %0 = shl i64 %Size, 2
; CHECK: %0 = shl nuw i64 %Size, 2
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %Base1, i8 1, i64 %0, i1 false)
; CHECK-NOT: store
}
@ -212,7 +212,7 @@ for.end: ; preds = %for.body, %entry
; CHECK-LABEL: @test6_dest_align(
; CHECK: %[[Dst:.*]] = bitcast i32* %Dest to i8*
; CHECK: %[[Src:.*]] = bitcast i32* %Base to i8*
; CHECK: %[[Sz:[0-9]+]] = shl i64 %Size, 2
; CHECK: %[[Sz:[0-9]+]] = shl nuw i64 %Size, 2
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[Dst]], i8* align 1 %[[Src]], i64 %[[Sz]], i1 false)
; CHECK-NOT: store
; CHECK: ret void
@ -238,7 +238,7 @@ for.end: ; preds = %for.body, %entry
; CHECK-LABEL: @test6_src_align(
; CHECK: %[[Dst]] = bitcast i32* %Dest to i8*
; CHECK: %[[Src]] = bitcast i32* %Base to i8*
; CHECK: %[[Sz:[0-9]+]] = shl i64 %Size, 2
; CHECK: %[[Sz:[0-9]+]] = shl nuw i64 %Size, 2
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %[[Dst]], i8* align 4 %[[Src]], i64 %[[Sz]], i1 false)
; CHECK-NOT: store
; CHECK: ret void
@ -653,7 +653,7 @@ loop.ph:
br label %loop.body
; CHECK: loop.ph:
; CHECK-NEXT: %[[ZEXT_SIZE:.*]] = zext i32 %size to i64
; CHECK-NEXT: %[[SCALED_SIZE:.*]] = shl i64 %[[ZEXT_SIZE]], 3
; CHECK-NEXT: %[[SCALED_SIZE:.*]] = shl nuw nsw i64 %[[ZEXT_SIZE]], 3
; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 %{{.*}}, i8 0, i64 %[[SCALED_SIZE]], i1 false)
loop.body:
@ -685,7 +685,7 @@ loop.ph:
br label %loop.body
; CHECK: loop.ph:
; CHECK-NEXT: %[[ZEXT_SIZE:.*]] = zext i32 %size to i64
; CHECK-NEXT: %[[SCALED_SIZE:.*]] = shl i64 %[[ZEXT_SIZE]], 3
; CHECK-NEXT: %[[SCALED_SIZE:.*]] = shl nuw nsw i64 %[[ZEXT_SIZE]], 3
; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %{{.*}}, i8* align 8 %{{.*}}, i64 %[[SCALED_SIZE]], i1 false)
loop.body:

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@ -13,7 +13,7 @@ define void @test6_dest_align(i32* noalias align 1 %Base, i32* noalias align 4 %
; CHECK-NEXT: bb.nph:
; CHECK-NEXT: [[DEST1:%.*]] = bitcast i32* [[DEST:%.*]] to i8*
; CHECK-NEXT: [[BASE2:%.*]] = bitcast i32* [[BASE:%.*]] to i8*
; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[SIZE:%.*]], 2, !dbg !18
; CHECK-NEXT: [[TMP0:%.*]] = shl nuw i64 [[SIZE:%.*]], 2, !dbg !18
; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[DEST1]], i8* align 1 [[BASE2]], i64 [[TMP0]], i1 false), !dbg !19
; CHECK-NEXT: br label [[FOR_BODY:%.*]], !dbg !18
; CHECK: for.body:

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@ -745,7 +745,7 @@ define void @pointer_bitcast_baseinst(i16* %arg, i8* %arg1, i64 %arg2) {
; CHECK-LABEL: @pointer_bitcast_baseinst(
; CHECK: bb3:
; CHECK-NEXT: %indvar = phi i64 [ %indvar.next, %bb3 ], [ 0, %bb ]
; CHECK-NEXT: %4 = shl i64 %indvar, 3
; CHECK-NEXT: %4 = shl nuw i64 %indvar, 3
; CHECK-NEXT: %5 = add i64 %4, 1
; CHECK-NEXT: %tmp5 = shl nuw i64 %5, 1
; CHECK-NEXT: %tmp6 = getelementptr i8, i8* %arg1, i64 %tmp5

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@ -104,7 +104,7 @@ while.body: ; preds = %while.body.preheade
;CHECK-NEXT: %indvar = phi i64 [ %indvar.next, %while.body ], [ 0, %while.body.preheader ]
;CHECK-NEXT: %S.012 = phi i32 [ %add, %while.body ], [ undef, %while.body.preheader ]
;CHECK-NEXT: %4 = trunc i64 %indvar to i32
;CHECK-NEXT: %5 = mul i64 %indvar, -1
;CHECK-NEXT: %5 = mul nsw i64 %indvar, -1
;CHECK-NEXT: %scevgep = getelementptr i32, i32* %buf, i64 %5
;CHECK-NEXT: %6 = load i32, i32* %scevgep, align 4
;CHECK-NEXT: %add = add nsw i32 %6, %S.012

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@ -52,7 +52,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: %0 = add i32 %n, -1
; CHECK: %1 = sub i32 %0, %m
; CHECK: %2 = lshr i32 %1, 2
; CHECK: %3 = shl i32 %2, 2
; CHECK: %3 = shl nuw i32 %2, 2
; CHECK: %4 = add i32 %3, 3
; CHECK: br label %for.body
@ -131,7 +131,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: %0 = add i32 %n, -1
; CHECK: %1 = sub i32 %0, %rem
; CHECK: %2 = lshr i32 %1, 2
; CHECK: %3 = shl i32 %2, 2
; CHECK: %3 = shl nuw i32 %2, 2
; CHECK: %4 = add i32 %3, 3
; CHECK: br label %for.body

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@ -52,7 +52,7 @@ while.body:
;CHECK-LABEL: while.body:
;CHECK-NEXT: %indvar = phi i64 [ %indvar.next, %while.body ], [ 0, %while.body.preheader ]
;CHECK-NEXT: %S.011 = phi i32 [ %add, %while.body ], [ undef, %while.body.preheader ]
;CHECK-NEXT: %4 = mul i64 %indvar, -1
;CHECK-NEXT: %4 = mul nsw i64 %indvar, -1
;CHECK-NEXT: %scevgep = getelementptr i32, i32* %buf, i64 %4
;CHECK-NEXT: %5 = load i32, i32* %scevgep, align 4
;CHECK-NEXT: %add = add nsw i32 %5, %S.011

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@ -12,8 +12,8 @@ target datalayout = "n8:16:32:64"
; CHECK-LABEL: @test(
; multiplies are hoisted out of the loop
; CHECK: while.body.lr.ph:
; CHECK: shl i64
; CHECK: shl i64
; CHECK: shl nsw i64
; CHECK: shl nsw i64
; GEPs are ugly
; CHECK: while.body:
; CHECK: phi

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@ -8,7 +8,7 @@
; CHECK: [[r2:%[a-z0-9\.]+]] = lshr exact i64 [[r1]], 1
; CHECK: [[r3:%[a-z0-9\.]+]] = bitcast i64 [[r2]] to i64
; CHECK: for.body.lr.ph:
; CHECK: [[r4:%[a-z0-9]+]] = shl i64 [[r3]], 1
; CHECK: [[r4:%[a-z0-9]+]] = shl nuw i64 [[r3]], 1
; CHECK: br label %for.body
; CHECK: for.body:
; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ [[r4]], %for.body.lr.ph ]