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[X86][SSE] Generalized unsigned compares to support nonsplat constant vectors (PR39859)

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llvm-svn: 352283
This commit is contained in:
Simon Pilgrim 2019-01-26 16:40:03 +00:00
parent 3daa245550
commit 6162fba57c
3 changed files with 14 additions and 15 deletions
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17
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -19604,17 +19604,20 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
TLI.isOperationLegal(ISD::UMIN, VT)) { TLI.isOperationLegal(ISD::UMIN, VT)) {
// If we have a constant operand, increment/decrement it and change the // If we have a constant operand, increment/decrement it and change the
// condition to avoid an invert. // condition to avoid an invert.
// TODO: This could be extended to handle a non-splat constant by checking if (Cond == ISD::SETUGT &&
// that each element of the constant is not the max/null value. ISD::matchUnaryPredicate(Op1, [](ConstantSDNode *C) {
APInt C; return !C->getAPIntValue().isMaxValue();
if (Cond == ISD::SETUGT && isConstantSplat(Op1, C) && !C.isMaxValue()) { })) {
// X > C --> X >= (C+1) --> X == umax(X, C+1) // X > C --> X >= (C+1) --> X == umax(X, C+1)
Op1 = DAG.getConstant(C + 1, dl, VT); Op1 = DAG.getNode(ISD::ADD, dl, VT, Op1, DAG.getConstant(1, dl, VT));
Cond = ISD::SETUGE; Cond = ISD::SETUGE;
} }
if (Cond == ISD::SETULT && isConstantSplat(Op1, C) && !C.isNullValue()) { if (Cond == ISD::SETULT &&
ISD::matchUnaryPredicate(Op1, [](ConstantSDNode *C) {
return !C->getAPIntValue().isNullValue();
})) {
// X < C --> X <= (C-1) --> X == umin(X, C-1) // X < C --> X <= (C-1) --> X == umin(X, C-1)
Op1 = DAG.getConstant(C - 1, dl, VT); Op1 = DAG.getNode(ISD::SUB, dl, VT, Op1, DAG.getConstant(1, dl, VT));
Cond = ISD::SETULE; Cond = ISD::SETULE;
} }
bool Invert = false; bool Invert = false;

6
llvm/test/CodeGen/X86/sat-add.ll
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@ -551,11 +551,9 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat(<4 x i32
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46] ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46]
; SSE41-NEXT: paddd %xmm0, %xmm1 ; SSE41-NEXT: paddd %xmm0, %xmm1
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967252,4294967251,4294967250,4294967249] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967253,4294967252,4294967251,4294967250]
; SSE41-NEXT: pminud %xmm0, %xmm2 ; SSE41-NEXT: pmaxud %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm0
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: por %xmm1, %xmm0 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
%a = add <4 x i32> %x, <i32 43, i32 44, i32 45, i32 46> %a = add <4 x i32> %x, <i32 43, i32 44, i32 45, i32 46>

6
llvm/test/CodeGen/X86/vec_setcc-2.ll
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@ -511,11 +511,9 @@ define <4 x i1> @ugt_v4i32_nonsplat(<4 x i32> %x) {
; ;
; SSE41-LABEL: ugt_v4i32_nonsplat: ; SSE41-LABEL: ugt_v4i32_nonsplat:
; SSE41: ## %bb.0: ; SSE41: ## %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967253,4294967254,4294967255,4294967256] ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967254,4294967255,4294967256,4294967257]
; SSE41-NEXT: pminud %xmm0, %xmm1 ; SSE41-NEXT: pmaxud %xmm0, %xmm1
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
%cmp = icmp ugt <4 x i32> %x, <i32 -43, i32 -42, i32 -41, i32 -40> %cmp = icmp ugt <4 x i32> %x, <i32 -43, i32 -42, i32 -41, i32 -40>
ret <4 x i1> %cmp ret <4 x i1> %cmp