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https://github.com/capstone-engine/llvm-capstone.git
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Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted:
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
%reg1031<def> = MOVPC32r 0
%reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
%reg1028<def> = MOV32rr %EAX
%reg1029<def> = MOV32rr %EDX
%reg1030<def> = MOV32rr %ECX
%reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
%reg1025<def> = MOV32rr %reg1029
%reg1026<def> = MOV32rr %reg1030
%reg1024<def> = MOV32rr %reg1028
The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.
With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
%reg1031<def> = MOVPC32r 0
%reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
%reg1024<def> = MOV32rr %EAX
%reg1025<def> = MOV32rr %EDX
%reg1026<def> = MOV32rr %ECX
%reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]
Much better!
llvm-svn: 48307
This commit is contained in:
Evan Cheng
parent
e2f6d6cdb8
commit
65e9d5f1a8
@ -15,7 +15,9 @@
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#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
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#define LLVM_CODEGEN_SCHEDULEDAG_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/SmallSet.h"
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@ -245,7 +247,7 @@ namespace llvm {
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const TargetInstrInfo *TII; // Target instruction information
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const TargetRegisterInfo *TRI; // Target processor register info
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MachineFunction *MF; // Machine function
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MachineRegisterInfo &RegInfo; // Virtual/real register map
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MachineRegisterInfo &MRI; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
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// represent noop instructions.
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@ -347,6 +349,22 @@ namespace llvm {
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const TargetInstrDesc &II,
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DenseMap<SDOperand, unsigned> &VRBaseMap);
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible. It returns the destination register of the emitted copy
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/// if it is a physical register; otherwise it returns zero.
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unsigned EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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BitVector &LiveRegsBefore,
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BitVector &LiveRegsAfter);
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/// EmitLiveInCopies - If this is the first basic block in the function,
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/// and if it has live ins that need to be copied into vregs, emit the
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/// copies into the top of the block.
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void EmitLiveInCopies(MachineBasicBlock *MBB);
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void EmitSchedule();
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void dumpSchedule() const;
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@ -25,15 +25,23 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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STATISTIC(NumCommutes, "Number of instructions commuted");
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namespace {
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static cl::opt<bool>
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SchedLiveInCopies("schedule-livein-copies",
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cl::desc("Schedule copies of livein registers"),
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cl::init(false));
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}
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ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
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: DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
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TII = TM.getInstrInfo();
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MF = &DAG.getMachineFunction();
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TRI = TM.getRegisterInfo();
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@ -437,7 +445,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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// Figure out the register class to create for the destreg.
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if (VRBase) {
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DstRC = RegInfo.getRegClass(VRBase);
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DstRC = MRI.getRegClass(VRBase);
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} else {
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DstRC = DAG.getTargetLoweringInfo()
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.getRegClassFor(Node->getValueType(ResNo));
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@ -449,7 +457,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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VRBase = SrcReg;
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} else {
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// Create the reg, emit the copy.
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VRBase = RegInfo.createVirtualRegister(DstRC);
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VRBase = MRI.createVirtualRegister(DstRC);
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TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
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}
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@ -488,7 +496,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
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if (VRBase == 0) {
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
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assert(RC && "Isn't a register operand!");
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VRBase = RegInfo.createVirtualRegister(RC);
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VRBase = MRI.createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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@ -539,7 +547,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
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assert((RC || II->isVariadic()) && "Expected reg class info!");
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const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
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const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
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if (RC && VRC != RC) {
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cerr << "Register class of operand and regclass of use don't agree!\n";
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cerr << "Operand = " << IIOpNum << "\n";
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@ -675,18 +683,18 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
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// Figure out the register class to create for the destreg.
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unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
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const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg);
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const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
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if (VRBase) {
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// Grab the destination register
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const TargetRegisterClass *DRC = RegInfo.getRegClass(VRBase);
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const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
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assert(SRC && DRC && SRC == DRC &&
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"Source subregister and destination must have the same class");
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} else {
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// Create the reg
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assert(SRC && "Couldn't find source register class");
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VRBase = RegInfo.createVirtualRegister(SRC);
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VRBase = MRI.createVirtualRegister(SRC);
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}
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// Add def, source, and subreg index
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@ -728,12 +736,12 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
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// Figure out the register class to create for the destreg.
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const TargetRegisterClass *TRC = 0;
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if (VRBase) {
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TRC = RegInfo.getRegClass(VRBase);
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TRC = MRI.getRegClass(VRBase);
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} else {
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TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx,
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TRC = getSuperregRegisterClass(MRI.getRegClass(SubReg), SubIdx,
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Node->getValueType(0));
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assert(TRC && "Couldn't determine register class for insert_subreg");
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VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg
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VRBase = MRI.createVirtualRegister(TRC); // Create the reg
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}
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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@ -858,12 +866,12 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
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const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
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// Get the register classes of the src/dst.
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if (TargetRegisterInfo::isVirtualRegister(SrcReg))
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SrcTRC = RegInfo.getRegClass(SrcReg);
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SrcTRC = MRI.getRegClass(SrcReg);
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else
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SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
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if (TargetRegisterInfo::isVirtualRegister(DestReg))
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DstTRC = RegInfo.getRegClass(DestReg);
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DstTRC = MRI.getRegClass(DestReg);
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else
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DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
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Node->getOperand(1).getValueType());
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@ -969,7 +977,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
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} else {
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// Copy from physical register.
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assert(I->Reg && "Unknown physical register!");
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unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
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unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
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bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
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assert(isNew && "Node emitted out of order - early");
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TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
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@ -979,22 +987,169 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
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}
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}
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/// regIsLive - Return true if the specified register is live due to a
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/// live in copy.
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static bool regIsLive(unsigned Reg, BitVector &LiveRegs,
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const TargetRegisterInfo *TRI) {
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if (LiveRegs[Reg])
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return true;
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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if (LiveRegs[*AS])
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return true;
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return false;
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}
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/// regIsClobbered - Return true if the specified register is defined in
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/// between the two specific instructions.
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static bool regIsClobbered(unsigned Reg, MachineBasicBlock *MBB,
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MachineBasicBlock::iterator InsertPos,
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MachineBasicBlock::iterator UsePos,
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const TargetRegisterInfo *TRI) {
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for (MachineBasicBlock::iterator I = InsertPos; I != UsePos; ++I) {
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MachineInstr *MI = I;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || !MO.isDef())
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continue;
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unsigned DefReg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(DefReg))
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continue;
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if (TRI->regsOverlap(DefReg, Reg))
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return true;
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}
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}
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return false;
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}
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/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
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/// physical register has only a single copy use, then coalesced the copy
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/// if possible. It returns the destination register of the emitted copy
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/// if it is a physical register; otherwise it returns zero.
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unsigned ScheduleDAG::EmitLiveInCopy(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &InsertPos,
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unsigned VirtReg, unsigned PhysReg,
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const TargetRegisterClass *RC,
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BitVector &LiveRegsBefore,
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BitVector &LiveRegsAfter) {
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unsigned NumUses = 0;
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MachineInstr *UseMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
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UE = MRI.use_end(); UI != UE; ++UI) {
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UseMI = &*UI;
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if (++NumUses > 1)
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break;
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}
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// If the number of uses is not one, or the use is not a move instruction,
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// don't coalesce.
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unsigned SrcReg, DstReg;
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if (NumUses != 1 ||
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!TII->isMoveInstr(*UseMI, SrcReg, DstReg)) {
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TII->copyRegToReg(*MBB, InsertPos, VirtReg, PhysReg, RC, RC);
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return 0;
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}
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// Coalesce away a virtual register to virtual register copy.
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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TII->copyRegToReg(*MBB, InsertPos, DstReg, PhysReg, RC, RC);
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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return 0;
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}
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// If the destination is a physical register, check if it's safe to
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// coalesce. If there is a def of the register between the insertion point and
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// the use, then it's not safe.
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if (regIsClobbered(DstReg, MBB, InsertPos, UseMI, TRI)) {
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TII->copyRegToReg(*MBB, InsertPos, VirtReg, PhysReg, RC, RC);
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return 0;
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}
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// Also check already processed livein copies and determine the safe location
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// to insert the copy. e.g. Suppose livein r0 is already processed and now
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// we are inserting r1 copy to vr1025 which will be coalesced to r0.
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// vr1024 = r0
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// <this is the insertion pt>
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// ...
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// It's safe to insert the copy from r1 to r0.
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// vr1024 = r0
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// r0 = r1
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//
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// However, if livein r0 copy is coalesced to r1:
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// r1 = r0
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// <insertion pt>
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// ...
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// Then it's not safe to insert the copy from r1 to r0 at the insertion pt.
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// Nor is it safe to insert it at the start of the MBB.
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//
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// If livein r3 is already processed and it's coalesced to r1.
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// <begin of MBB> -- safe to insert here
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// r1 = r3
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// <insertion pt> -- not safe
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// Then it's safe to insert at the start of the MBB.
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if (regIsLive(DstReg, LiveRegsAfter, TRI)) {
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if (regIsLive(PhysReg, LiveRegsBefore, TRI)) {
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// FIXME: Still possible to find a safe place to insert the copy.
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TII->copyRegToReg(*MBB, InsertPos, VirtReg, PhysReg, RC, RC);
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return 0;
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}
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TII->copyRegToReg(*MBB, MBB->begin(), DstReg, PhysReg, RC, RC);
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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return DstReg;
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}
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TII->copyRegToReg(*MBB, InsertPos, DstReg, PhysReg, RC, RC);
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if (&*InsertPos == UseMI) ++InsertPos;
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MBB->erase(UseMI);
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return DstReg;
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}
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/// EmitLiveInCopies - If this is the first basic block in the function,
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/// and if it has live ins that need to be copied into vregs, emit the
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/// copies into the top of the block.
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void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
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BitVector LiveRegsBefore; // Live registers before insertion pt.
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BitVector LiveRegsAfter; // Live registers after insertion pt.
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LiveRegsBefore.resize(TRI->getNumRegs());
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LiveRegsAfter.resize(TRI->getNumRegs());
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MachineBasicBlock::iterator InsertPos = MBB->begin();
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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unsigned Reg = EmitLiveInCopy(MBB, InsertPos, LI->second, LI->first, RC,
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LiveRegsBefore, LiveRegsAfter);
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if (Reg) {
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LiveRegsAfter.set(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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LiveRegsAfter.set(SubReg);
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}
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LiveRegsBefore.set(LI->first);
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for (const unsigned *SubRegs = TRI->getSubRegisters(LI->first);
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unsigned SubReg = *SubRegs; ++SubRegs)
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LiveRegsBefore.set(SubReg);
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}
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}
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/// EmitSchedule - Emit the machine code in scheduled order.
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void ScheduleDAG::EmitSchedule() {
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// If this is the first basic block in the function, and if it has live ins
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// that need to be copied into vregs, emit the copies into the top of the
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// block before emitting the code for the block.
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if (&MF->front() == BB) {
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for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
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E = RegInfo.livein_end(); LI != E; ++LI)
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bool isEntryBB = &MF->front() == BB;
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if (isEntryBB && !SchedLiveInCopies) {
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// If this is the first basic block in the function, and if it has live ins
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// that need to be copied into vregs, emit the copies into the top of the
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// block before emitting the code for the block.
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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E = MRI.livein_end(); LI != E; ++LI)
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if (LI->second) {
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const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
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const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
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TII->copyRegToReg(*MF->begin(), MF->begin()->end(), LI->second,
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LI->first, RC, RC);
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}
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}
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// Finally, emit the code for all of the scheduled instructions.
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DenseMap<SDOperand, unsigned> VRBaseMap;
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DenseMap<SUnit*, unsigned> CopyVRBaseMap;
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@ -1011,6 +1166,9 @@ void ScheduleDAG::EmitSchedule() {
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EmitNoop();
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}
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}
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if (isEntryBB && SchedLiveInCopies)
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EmitLiveInCopies(MF->begin());
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}
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/// dump - dump the schedule.
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@ -1,4 +1,5 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim
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; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim -schedule-livein-copies | not grep {Number of register spills}
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; PR2134
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declare fastcc i8* @w_addchar(i8*, i32*, i32*, i8 signext ) nounwind
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