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https://github.com/capstone-engine/llvm-capstone.git
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Add 256-bit load/store recognition and matching in several places.
llvm-svn: 135171
This commit is contained in:
Bruno Cardoso Lopes
parent
2dc4b55bd8
commit
6778597deb
@ -301,12 +301,17 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
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{ X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
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{ X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
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{ X86::VMOVAPDYrr, X86::VMOVAPDYmr, 0, 32 },
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{ X86::VMOVAPSYrr, X86::VMOVAPSYmr, 0, 32 },
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{ X86::VMOVDQAYrr, X86::VMOVDQAYmr, 0, 32 },
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{ X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
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{ X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
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{ X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
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{ X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
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{ X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
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{ X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
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{ X86::VMOVUPDYrr, X86::VMOVUPDYmr, 0, 0 },
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{ X86::VMOVUPSYrr, X86::VMOVUPSYmr, 0, 0 },
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{ X86::MUL16r, X86::MUL16m, 1, 0 },
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{ X86::MUL32r, X86::MUL32m, 1, 0 },
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{ X86::MUL64r, X86::MUL64m, 1, 0 },
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@ -411,10 +416,13 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::MOV8rr, X86::MOV8rm, 0 },
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{ X86::MOVAPDrr, X86::MOVAPDrm, 16 },
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{ X86::MOVAPSrr, X86::MOVAPSrm, 16 },
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{ X86::VMOVAPDYrr, X86::VMOVAPDYrm, 32 },
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{ X86::VMOVAPSYrr, X86::VMOVAPSYrm, 32 },
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{ X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
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{ X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
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{ X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
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{ X86::MOVDQArr, X86::MOVDQArm, 16 },
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{ X86::VMOVDQAYrr, X86::VMOVDQAYrm, 16 },
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{ X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
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{ X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
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{ X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
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@ -425,6 +433,8 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
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{ X86::MOVUPDrr, X86::MOVUPDrm, 16 },
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{ X86::MOVUPSrr, X86::MOVUPSrm, 0 },
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{ X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
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{ X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
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{ X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
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{ X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
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{ X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
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@ -787,6 +797,9 @@ static bool isFrameLoadOpcode(int Opcode) {
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case X86::MOVAPSrm:
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case X86::MOVAPDrm:
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case X86::MOVDQArm:
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case X86::VMOVAPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVDQAYrm:
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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return true;
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@ -808,6 +821,9 @@ static bool isFrameStoreOpcode(int Opcode) {
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case X86::MOVAPSmr:
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case X86::MOVAPDmr:
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case X86::MOVDQAmr:
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case X86::VMOVAPSYmr:
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case X86::VMOVAPDYmr:
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case X86::VMOVDQAYmr:
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case X86::MMX_MOVD64mr:
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case X86::MMX_MOVQ64mr:
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case X86::MMX_MOVNTQmr:
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@ -926,6 +942,10 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
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case X86::MOVUPSrm:
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case X86::MOVAPDrm:
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case X86::MOVDQArm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVDQAYrm:
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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case X86::FsMOVAPSrm:
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@ -1975,6 +1995,8 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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Opc = X86::MOV8rr;
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} else if (X86::VR128RegClass.contains(DestReg, SrcReg))
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Opc = X86::MOVAPSrr;
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else if (X86::VR256RegClass.contains(DestReg, SrcReg))
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Opc = X86::VMOVAPSYrr;
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else if (X86::VR64RegClass.contains(DestReg, SrcReg))
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Opc = X86::MMX_MOVQ64rr;
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else
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@ -2064,6 +2086,13 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
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return load ? X86::MOVAPSrm : X86::MOVAPSmr;
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else
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return load ? X86::MOVUPSrm : X86::MOVUPSmr;
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case 32:
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assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
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// If stack is realigned we can use aligned stores.
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if (isStackAligned)
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return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
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else
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return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
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}
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}
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@ -2853,6 +2882,11 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::MOVAPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVDQAYrm:
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case X86::VMOVDQUYrm:
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break;
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}
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switch (Opc2) {
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@ -2875,6 +2909,11 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::MOVAPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVDQAYrm:
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case X86::VMOVDQUYrm:
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break;
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}
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@ -3053,6 +3092,13 @@ static const unsigned ReplaceableInstrs[][3] = {
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{ X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
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{ X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
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{ X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
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// AVX 256-bit support
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{ X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
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{ X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
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{ X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
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{ X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
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{ X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
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{ X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
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};
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// FIXME: Some shuffle and unpack instructions have equivalents in different
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@ -2022,7 +2022,10 @@ def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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}
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// The same as done above but for AVX. The 128-bit versions are the
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// same, but re-encoded. The 256-bit does not support PI version.
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// same, but re-encoded. The 256-bit does not support PI version, and
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// doesn't need it because on sandy bridge the register is set to zero
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// at the rename stage without using any execution unit, so SET0PSY
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// and SET0PDY can be used for vector int instructions without penalty
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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// JIT implementatioan, it does not expand the instructions below like
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// X86MCInstLower does.
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@ -2037,8 +2040,8 @@ def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
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let ExeDomain = SSEPackedInt in
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def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllZerosV))]>;
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def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllZerosV))]>;
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}
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def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
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@ -3831,6 +3834,8 @@ def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
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(CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
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// Use movaps / movups for SSE integer load / store (one byte shorter).
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// The instructions selected below are then converted to MOVDQA/MOVDQU
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// during the SSE domain pass.
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let Predicates = [HasSSE1] in {
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def : Pat<(alignedloadv4i32 addr:$src),
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(MOVAPSrm addr:$src)>;
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@ -3859,8 +3864,9 @@ let Predicates = [HasSSE1] in {
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(MOVUPSmr addr:$dst, VR128:$src)>;
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}
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// Use vmovaps/vmovups for AVX 128-bit integer load/store (one byte shorter).
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// Use vmovaps/vmovups for AVX integer load/store.
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let Predicates = [HasAVX] in {
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// 128-bit load/store
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def : Pat<(alignedloadv4i32 addr:$src),
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(VMOVAPSrm addr:$src)>;
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def : Pat<(loadv4i32 addr:$src),
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@ -3886,6 +3892,24 @@ let Predicates = [HasAVX] in {
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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// 256-bit load/store
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def : Pat<(alignedloadv4i64 addr:$src),
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(VMOVAPSYrm addr:$src)>;
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def : Pat<(loadv4i64 addr:$src),
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(VMOVUPSYrm addr:$src)>;
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def : Pat<(alignedloadv8i32 addr:$src),
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(VMOVAPSYrm addr:$src)>;
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def : Pat<(loadv8i32 addr:$src),
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(VMOVUPSYrm addr:$src)>;
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def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v4i64 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v8i32 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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}
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//===----------------------------------------------------------------------===//
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24
llvm/test/CodeGen/X86/avx-load-store.ll
Normal file
24
llvm/test/CodeGen/X86/avx-load-store.ll
Normal file
@ -0,0 +1,24 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vmovaps
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; CHECK: vmovaps
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; CHECK: vmovapd
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; CHECK: vmovapd
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; CHECK: vmovaps
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; CHECK: vmovaps
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define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind uwtable ssp {
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entry:
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%0 = bitcast double* %d to <4 x double>*
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%tmp1.i = load <4 x double>* %0, align 32
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%1 = bitcast float* %f to <8 x float>*
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%tmp1.i17 = load <8 x float>* %1, align 32
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%tmp1.i16 = load <4 x i64>* %i, align 32
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tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind
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store <4 x double> %tmp1.i, <4 x double>* %0, align 32
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store <8 x float> %tmp1.i17, <8 x float>* %1, align 32
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store <4 x i64> %tmp1.i16, <4 x i64>* %i, align 32
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ret void
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}
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declare void @dummy(<4 x double>, <8 x float>, <4 x i64>)
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