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AMDGPU/GlobalISel: Legalize G_FRINT
llvm-svn: 361026
This commit is contained in:
Matt Arsenault
parent
1448f5689e
commit
6aafc5e19d
@ -293,6 +293,18 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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.legalFor({S32, S64})
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.scalarize(0);
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if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
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getActionDefinitionsBuilder(G_FRINT)
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.legalFor({S32, S64})
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.clampScalar(0, S32, S64)
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.scalarize(0);
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} else {
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getActionDefinitionsBuilder(G_FRINT)
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.legalFor({S32})
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.customFor({S64})
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.clampScalar(0, S32, S64)
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.scalarize(0);
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}
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getActionDefinitionsBuilder(G_GEP)
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.legalForCartesianProduct(AddrSpaces64, {S64})
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@ -675,6 +687,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
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switch (MI.getOpcode()) {
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case TargetOpcode::G_ADDRSPACE_CAST:
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return legalizeAddrSpaceCast(MI, MRI, MIRBuilder);
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case TargetOpcode::G_FRINT:
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return legalizeFrint(MI, MRI, MIRBuilder);
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default:
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return false;
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}
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@ -831,3 +845,30 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
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MI.eraseFromParent();
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeFrint(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MIRBuilder.setInstr(MI);
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unsigned Src = MI.getOperand(1).getReg();
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LLT Ty = MRI.getType(Src);
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assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
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APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
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APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
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auto C1 = MIRBuilder.buildFConstant(Ty, C1Val);
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auto CopySign = MIRBuilder.buildFCopysign(Ty, C1, Src);
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// TODO: Should this propagate fast-math-flags?
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auto Tmp1 = MIRBuilder.buildFAdd(Ty, Src, CopySign);
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auto Tmp2 = MIRBuilder.buildFSub(Ty, Tmp1, CopySign);
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auto C2 = MIRBuilder.buildFConstant(Ty, C2Val);
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auto Fabs = MIRBuilder.buildFAbs(Ty, Src);
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auto Cond = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
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MIRBuilder.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
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return true;
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}
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@ -38,6 +38,9 @@ public:
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bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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};
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} // End llvm namespace.
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#endif
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160
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
Normal file
160
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
Normal file
@ -0,0 +1,160 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer -o - %s | FileCheck -check-prefix=CI %s
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---
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name: test_frint_s16
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_frint_s16
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
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; SI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
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; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
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; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
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; SI: $vgpr0 = COPY [[ANYEXT]](s32)
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; CI-LABEL: name: test_frint_s16
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; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
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; CI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
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; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
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; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
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; CI: $vgpr0 = COPY [[ANYEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s16) = G_FRINT %1
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%3:_(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: test_frint_s32
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_frint_s32
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: $vgpr0 = COPY [[COPY]](s32)
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; CI-LABEL: name: test_frint_s32
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; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CI: $vgpr0 = COPY [[COPY]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_FRINT %0
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$vgpr0 = COPY %0
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...
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---
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name: test_frint_s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_frint_s64
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; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; SI: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[C]], [[COPY]](s64)
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; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FCOPYSIGN]]
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; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FCOPYSIGN]]
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; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
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; SI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
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; SI: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
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; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C1]]
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; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FADD1]]
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; SI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
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; SI: $vgpr0_vgpr1 = COPY [[FRINT]](s64)
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; CI-LABEL: name: test_frint_s64
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; CI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
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; CI: $vgpr0_vgpr1 = COPY [[FRINT]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_FRINT %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_frint_v2s16
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_frint_v2s16
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; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
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; CI-LABEL: name: test_frint_v2s16
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; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s16>) = G_FRINT %0
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$vgpr0 = COPY %0
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...
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---
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name: test_frint_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_frint_v2s32
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; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; SI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[UV]]
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; SI: [[FRINT1:%[0-9]+]]:_(s32) = G_FRINT [[UV1]]
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; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FRINT]](s32), [[FRINT1]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; CI-LABEL: name: test_frint_v2s32
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; CI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[UV]]
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; CI: [[FRINT1:%[0-9]+]]:_(s32) = G_FRINT [[UV1]]
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; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FRINT]](s32), [[FRINT1]](s32)
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; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = G_FRINT %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_frint_v2s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; SI-LABEL: name: test_frint_v2s64
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; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; SI: [[FCOPYSIGN:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[C]], [[UV]](s64)
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; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FCOPYSIGN]]
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; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FCOPYSIGN]]
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; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
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; SI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
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; SI: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[UV]]
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; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C1]]
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; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FADD1]]
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; SI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[UV]]
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; SI: [[FCOPYSIGN1:%[0-9]+]]:_(s64) = G_FCOPYSIGN [[C]], [[UV1]](s64)
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; SI: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FCOPYSIGN1]]
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; SI: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[FCOPYSIGN1]]
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; SI: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[FADD2]], [[FNEG1]]
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; SI: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[UV1]]
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; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS1]](s64), [[C1]]
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; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](s1), [[UV1]], [[FADD3]]
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; SI: [[FRINT1:%[0-9]+]]:_(s64) = G_FRINT [[UV1]]
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; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FRINT]](s64), [[FRINT1]](s64)
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; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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; CI-LABEL: name: test_frint_v2s64
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; CI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; CI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[UV]]
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; CI: [[FRINT1:%[0-9]+]]:_(s64) = G_FRINT [[UV1]]
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; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FRINT]](s64), [[FRINT1]](s64)
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; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<2 x s64>) = G_FRINT %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
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...
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