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[VE] Change to use R_VE_SREL32
Change to use R_VE_SREL32 for relative branch instructions instead of R_VE_PC_LO32 in order to check ranges of relative branch isntructions at link time correctly. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D115097
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@ -42,6 +42,7 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
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case VE::fixup_ve_tpoff_hi32:
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return (Value >> 32) & 0xffffffff;
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case VE::fixup_ve_reflong:
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case VE::fixup_ve_srel32:
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case VE::fixup_ve_lo32:
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case VE::fixup_ve_pc_lo32:
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case VE::fixup_ve_got_lo32:
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@ -68,6 +69,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case FK_Data_4:
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case FK_PCRel_4:
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case VE::fixup_ve_reflong:
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case VE::fixup_ve_srel32:
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case VE::fixup_ve_hi32:
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case VE::fixup_ve_lo32:
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case VE::fixup_ve_pc_hi32:
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@ -103,6 +105,7 @@ public:
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const static MCFixupKindInfo Infos[VE::NumTargetFixupKinds] = {
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// name, offset, bits, flags
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{"fixup_ve_reflong", 0, 32, 0},
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{"fixup_ve_srel32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_ve_hi32", 0, 32, 0},
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{"fixup_ve_lo32", 0, 32, 0},
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{"fixup_ve_pc_hi32", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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@ -56,6 +56,8 @@ unsigned VEELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
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return ELF::R_VE_REFLONG;
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case FK_PCRel_8:
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return ELF::R_VE_REFQUAD;
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case VE::fixup_ve_srel32:
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return ELF::R_VE_SREL32;
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case VE::fixup_ve_pc_hi32:
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return ELF::R_VE_PC_HI32;
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case VE::fixup_ve_pc_lo32:
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@ -76,6 +78,8 @@ unsigned VEELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
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return ELF::R_VE_REFQUAD;
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case VE::fixup_ve_reflong:
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return ELF::R_VE_REFLONG;
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case VE::fixup_ve_srel32:
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llvm_unreachable("Unimplemented fixup pc_hi32 -> relocation");
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case VE::fixup_ve_hi32:
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return ELF::R_VE_HI32;
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case VE::fixup_ve_lo32:
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@ -17,6 +17,9 @@ enum Fixups {
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/// fixup_ve_reflong - 32-bit fixup corresponding to foo
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fixup_ve_reflong = FirstTargetFixupKind,
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/// fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
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fixup_ve_srel32,
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/// fixup_ve_hi32 - 32-bit fixup corresponding to foo@hi
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fixup_ve_hi32,
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@ -131,7 +131,7 @@ VEMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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return getMachineOpValue(MI, MO, Fixups, STI);
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Fixups.push_back(
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MCFixup::create(0, MO.getExpr(), (MCFixupKind)VE::fixup_ve_pc_lo32));
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MCFixup::create(0, MO.getExpr(), (MCFixupKind)VE::fixup_ve_srel32));
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return 0;
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}
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@ -11,6 +11,6 @@
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# CHECK-NEXT: b.l.t tgt+24(, %s1)
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# CHECK-OBJ: 0 R_VE_REFLONG tgt
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# CHECK-OBJ: 8 R_VE_PC_LO32 tgt2
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# CHECK-OBJ: 8 R_VE_SREL32 tgt2
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# CHECK-OBJ: 10 R_VE_REFLONG tgt
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# CHECK-OBJ: 18 R_VE_REFLONG tgt+0x18
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