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[RISCV][NFC] Unify CHECK lines for jumptable.ll @below_threshold test
These are all identical across XLEN and code model since they're not using a jump table, so unify them rather than having multiple copies.
This commit is contained in:
Jessica Clarke
parent
e0fe8e6412
commit
6e8bcaafba
@ -1,141 +1,45 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I-SMALL
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL
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; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM
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; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I-SMALL
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-SMALL
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; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I-MEDIUM
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM
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define void @below_threshold(i32 signext %in, ptr %out) nounwind {
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; RV32I-SMALL-LABEL: below_threshold:
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; RV32I-SMALL: # %bb.0: # %entry
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; RV32I-SMALL-NEXT: li a2, 2
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; RV32I-SMALL-NEXT: blt a2, a0, .LBB0_4
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; RV32I-SMALL-NEXT: # %bb.1: # %entry
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; RV32I-SMALL-NEXT: li a2, 1
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; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7
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; RV32I-SMALL-NEXT: # %bb.2: # %entry
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; RV32I-SMALL-NEXT: li a2, 2
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; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV32I-SMALL-NEXT: # %bb.3: # %bb2
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; RV32I-SMALL-NEXT: li a0, 3
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; RV32I-SMALL-NEXT: j .LBB0_9
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; RV32I-SMALL-NEXT: .LBB0_4: # %entry
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; RV32I-SMALL-NEXT: li a2, 3
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; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8
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; RV32I-SMALL-NEXT: # %bb.5: # %entry
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; RV32I-SMALL-NEXT: li a2, 4
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; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV32I-SMALL-NEXT: # %bb.6: # %bb4
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; RV32I-SMALL-NEXT: li a0, 1
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; RV32I-SMALL-NEXT: j .LBB0_9
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; RV32I-SMALL-NEXT: .LBB0_7: # %bb1
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; RV32I-SMALL-NEXT: li a0, 4
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; RV32I-SMALL-NEXT: j .LBB0_9
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; RV32I-SMALL-NEXT: .LBB0_8: # %bb3
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; RV32I-SMALL-NEXT: li a0, 2
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; RV32I-SMALL-NEXT: .LBB0_9: # %exit
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; RV32I-SMALL-NEXT: sw a0, 0(a1)
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; RV32I-SMALL-NEXT: .LBB0_10: # %exit
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; RV32I-SMALL-NEXT: ret
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;
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; RV32I-MEDIUM-LABEL: below_threshold:
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; RV32I-MEDIUM: # %bb.0: # %entry
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; RV32I-MEDIUM-NEXT: li a2, 2
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; RV32I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
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; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
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; RV32I-MEDIUM-NEXT: li a2, 1
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; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
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; RV32I-MEDIUM-NEXT: # %bb.2: # %entry
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; RV32I-MEDIUM-NEXT: li a2, 2
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; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV32I-MEDIUM-NEXT: # %bb.3: # %bb2
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; RV32I-MEDIUM-NEXT: li a0, 3
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; RV32I-MEDIUM-NEXT: j .LBB0_9
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; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry
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; RV32I-MEDIUM-NEXT: li a2, 3
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; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
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; RV32I-MEDIUM-NEXT: # %bb.5: # %entry
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; RV32I-MEDIUM-NEXT: li a2, 4
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; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV32I-MEDIUM-NEXT: # %bb.6: # %bb4
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; RV32I-MEDIUM-NEXT: li a0, 1
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; RV32I-MEDIUM-NEXT: j .LBB0_9
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; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb1
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; RV32I-MEDIUM-NEXT: li a0, 4
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; RV32I-MEDIUM-NEXT: j .LBB0_9
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; RV32I-MEDIUM-NEXT: .LBB0_8: # %bb3
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; RV32I-MEDIUM-NEXT: li a0, 2
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; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit
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; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
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; RV32I-MEDIUM-NEXT: .LBB0_10: # %exit
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; RV32I-MEDIUM-NEXT: ret
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;
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; RV64I-SMALL-LABEL: below_threshold:
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; RV64I-SMALL: # %bb.0: # %entry
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; RV64I-SMALL-NEXT: li a2, 2
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; RV64I-SMALL-NEXT: blt a2, a0, .LBB0_4
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; RV64I-SMALL-NEXT: # %bb.1: # %entry
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; RV64I-SMALL-NEXT: li a2, 1
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; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7
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; RV64I-SMALL-NEXT: # %bb.2: # %entry
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; RV64I-SMALL-NEXT: li a2, 2
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; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV64I-SMALL-NEXT: # %bb.3: # %bb2
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; RV64I-SMALL-NEXT: li a0, 3
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; RV64I-SMALL-NEXT: j .LBB0_9
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; RV64I-SMALL-NEXT: .LBB0_4: # %entry
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; RV64I-SMALL-NEXT: li a2, 3
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; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8
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; RV64I-SMALL-NEXT: # %bb.5: # %entry
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; RV64I-SMALL-NEXT: li a2, 4
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; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV64I-SMALL-NEXT: # %bb.6: # %bb4
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; RV64I-SMALL-NEXT: li a0, 1
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; RV64I-SMALL-NEXT: j .LBB0_9
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; RV64I-SMALL-NEXT: .LBB0_7: # %bb1
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; RV64I-SMALL-NEXT: li a0, 4
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; RV64I-SMALL-NEXT: j .LBB0_9
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; RV64I-SMALL-NEXT: .LBB0_8: # %bb3
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; RV64I-SMALL-NEXT: li a0, 2
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; RV64I-SMALL-NEXT: .LBB0_9: # %exit
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; RV64I-SMALL-NEXT: sw a0, 0(a1)
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; RV64I-SMALL-NEXT: .LBB0_10: # %exit
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; RV64I-SMALL-NEXT: ret
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;
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; RV64I-MEDIUM-LABEL: below_threshold:
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; RV64I-MEDIUM: # %bb.0: # %entry
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; RV64I-MEDIUM-NEXT: li a2, 2
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; RV64I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
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; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
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; RV64I-MEDIUM-NEXT: li a2, 1
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; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
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; RV64I-MEDIUM-NEXT: # %bb.2: # %entry
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; RV64I-MEDIUM-NEXT: li a2, 2
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; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV64I-MEDIUM-NEXT: # %bb.3: # %bb2
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; RV64I-MEDIUM-NEXT: li a0, 3
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; RV64I-MEDIUM-NEXT: j .LBB0_9
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; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry
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; RV64I-MEDIUM-NEXT: li a2, 3
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; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
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; RV64I-MEDIUM-NEXT: # %bb.5: # %entry
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; RV64I-MEDIUM-NEXT: li a2, 4
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; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV64I-MEDIUM-NEXT: # %bb.6: # %bb4
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; RV64I-MEDIUM-NEXT: li a0, 1
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; RV64I-MEDIUM-NEXT: j .LBB0_9
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; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb1
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; RV64I-MEDIUM-NEXT: li a0, 4
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; RV64I-MEDIUM-NEXT: j .LBB0_9
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; RV64I-MEDIUM-NEXT: .LBB0_8: # %bb3
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; RV64I-MEDIUM-NEXT: li a0, 2
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; RV64I-MEDIUM-NEXT: .LBB0_9: # %exit
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; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
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; RV64I-MEDIUM-NEXT: .LBB0_10: # %exit
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; RV64I-MEDIUM-NEXT: ret
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; CHECK-LABEL: below_threshold:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a2, 2
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; CHECK-NEXT: blt a2, a0, .LBB0_4
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: li a2, 1
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; CHECK-NEXT: beq a0, a2, .LBB0_7
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; CHECK-NEXT: # %bb.2: # %entry
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; CHECK-NEXT: li a2, 2
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; CHECK-NEXT: bne a0, a2, .LBB0_10
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; CHECK-NEXT: # %bb.3: # %bb2
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; CHECK-NEXT: li a0, 3
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; CHECK-NEXT: j .LBB0_9
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; CHECK-NEXT: .LBB0_4: # %entry
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; CHECK-NEXT: li a2, 3
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; CHECK-NEXT: beq a0, a2, .LBB0_8
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; CHECK-NEXT: # %bb.5: # %entry
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; CHECK-NEXT: li a2, 4
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; CHECK-NEXT: bne a0, a2, .LBB0_10
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; CHECK-NEXT: # %bb.6: # %bb4
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: j .LBB0_9
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; CHECK-NEXT: .LBB0_7: # %bb1
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; CHECK-NEXT: li a0, 4
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; CHECK-NEXT: j .LBB0_9
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; CHECK-NEXT: .LBB0_8: # %bb3
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; CHECK-NEXT: li a0, 2
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; CHECK-NEXT: .LBB0_9: # %exit
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; CHECK-NEXT: sw a0, 0(a1)
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; CHECK-NEXT: .LBB0_10: # %exit
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; CHECK-NEXT: ret
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entry:
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switch i32 %in, label %exit [
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i32 1, label %bb1
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