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[test][HWASAN] Regenerate some HWASAN tests

Browse Source 
Example of the command used to update tests:
```
ninja -C <build_dir> opt && llvm/utils/update_test_checks.py \
  --opt-binary <build_dir>/bin/opt llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
```

Reviewed By: kstoimenov

Differential Revision: https://reviews.llvm.org/D149219
This commit is contained in:
Vitaly Buka 2023-04-23 21:43:32 -07:00
parent 1f2d945f29
commit 6e8ce16797
20 changed files with 3087 additions and 704 deletions
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50
llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca-with-calls.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test alloca instrumentation when tags are generated by HWASan function.
;
; RUN: opt < %s -passes=hwasan -hwasan-generate-tags-with-calls -S | FileCheck %s
@ -8,12 +9,49 @@ target triple = "riscv64-unknown-linux"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[T1:[^ ]*]] = call i8 @__hwasan_generate_tag()
; CHECK: %[[A:[^ ]*]] = zext i8 %[[T1]] to i64
; CHECK: %[[B:[^ ]*]] = ptrtoint ptr %x to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[A]], 56
; CHECK: or i64 %[[B]], %[[C]]
; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44
; CHECK-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test_alloca to i64), [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]]
; CHECK-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP15:%.*]] = call i8 @__hwasan_generate_tag()
; CHECK-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP16]], 56
; CHECK-NEXT: [[TMP19:%.*]] = or i64 [[TMP17]], [[TMP18]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP19]] to ptr
; CHECK-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP16]] to i8
; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = lshr i64 [[TMP21]], 4
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP22]]
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[TMP23]], i32 0
; CHECK-NEXT: store i8 4, ptr [[TMP24]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[X]], i32 15
; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP25]], align 1
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 4
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP27]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP28]], i8 0, i64 1, i1 false)
; CHECK-NEXT: ret void
;
entry:
%x = alloca i32, align 4

137
llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
View File

@ -1,8 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test alloca instrumentation.
;
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,NO-UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=CHECK,ZERO-BASED-SHADOW,NO-UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -S | FileCheck %s --check-prefixes=DYNAMIC-SHADOW
; RUN: opt < %s -passes=hwasan -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=ZERO-BASED-SHADOW
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=DYNAMIC-SHADOW-UAR-TAGS
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux"
@ -10,44 +11,98 @@ target triple = "riscv64-unknown-linux"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress !dbg !15 {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56
; CHECK: %[[D:[^ ]*]] = or i64 %[[X1]], %[[C]]
; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to ptr
; CHECK: %[[X_TAG2:[^ ]*]] = trunc i64 %[[X_TAG]] to i8
; CHECK: %[[E:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[F:[^ ]*]] = lshr i64 %[[E]], 4
; DYNAMIC-SHADOW: %[[X_SHADOW:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %[[F]]
; ZERO-BASED-SHADOW: %[[X_SHADOW:[^ ]*]] = inttoptr i64 %[[F]] to ptr
; CHECK: %[[X_SHADOW_GEP:[^ ]*]] = getelementptr i8, ptr %[[X_SHADOW]], i32 0
; CHECK: store i8 4, ptr %[[X_SHADOW_GEP]]
; CHECK: %[[X_I8_GEP:[^ ]*]] = getelementptr i8, ptr %[[X]], i32 15
; CHECK: store i8 %[[X_TAG2]], ptr %[[X_I8_GEP]]
; CHECK: call void @llvm.dbg.value(
; CHECK-SAME: metadata !DIArgList(ptr %[[X]], ptr %[[X]])
; CHECK-SAME: metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0,
; CHECK: call void @use32(ptr nonnull %[[X_HWASAN]])
; UAR-TAGS: %[[BASE_TAG_COMPL:[^ ]*]] = xor i64 %[[BASE_TAG]], 255
; UAR-TAGS: %[[X_TAG_UAR:[^ ]*]] = trunc i64 %[[BASE_TAG_COMPL]] to i8
; CHECK: %[[E2:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[F2:[^ ]*]] = lshr i64 %[[E2]], 4
; DYNAMIC-SHADOW: %[[X_SHADOW2:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %[[F2]]
; ZERO-BASED-SHADOW: %[[X_SHADOW2:[^ ]*]] = inttoptr i64 %[[F2]] to ptr
; NO-UAR-TAGS: call void @llvm.memset.p0.i64(ptr align 1 %[[X_SHADOW2]], i8 0, i64 1, i1 false)
; UAR-TAGS: call void @llvm.memset.p0.i64(ptr align 1 %[[X_SHADOW2]], i8 %[[X_TAG_UAR]], i64 1, i1 false)
; CHECK: ret void
; DYNAMIC-SHADOW-LABEL: define void @test_alloca
; DYNAMIC-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; DYNAMIC-SHADOW-NEXT: entry:
; DYNAMIC-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; DYNAMIC-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; DYNAMIC-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; DYNAMIC-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; DYNAMIC-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; DYNAMIC-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; DYNAMIC-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 4, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP9]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 4, ptr [[TMP11]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 [[TMP7]], ptr [[TMP12]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP13]], 4, !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP14]], !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP15]], i8 0, i64 1, i1 false), !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: ret void, !dbg [[DBG14]]
;
; ZERO-BASED-SHADOW-LABEL: define void @test_alloca
; ZERO-BASED-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; ZERO-BASED-SHADOW-NEXT: entry:
; ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ZERO-BASED-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; ZERO-BASED-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; ZERO-BASED-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; ZERO-BASED-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; ZERO-BASED-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]], !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 4, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 4, ptr [[TMP11]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 [[TMP7]], ptr [[TMP12]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP13]], 4, !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP15]], i8 0, i64 1, i1 false), !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: ret void, !dbg [[DBG14]]
;
; DYNAMIC-SHADOW-UAR-TAGS-LABEL: define void @test_alloca
; DYNAMIC-SHADOW-UAR-TAGS-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: entry:
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 4, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP9]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: store i8 4, ptr [[TMP11]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: store i8 [[TMP7]], ptr [[TMP12]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP13:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 255, !dbg [[DBG14:![0-9]+]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8, !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP15]], 4, !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP16]], !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP17]], i8 [[TMP14]], i64 1, i1 false), !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: ret void, !dbg [[DBG14]]
;
entry:
%x = alloca i32, align 4
call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21

33
llvm/test/Instrumentation/HWAddressSanitizer/RISCV/atomic.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test basic address sanitizer instrumentation.
;
; RUN: opt < %s -passes=hwasan -S | FileCheck %s
@ -6,10 +7,18 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux"
define void @atomicrmw(ptr %ptr) sanitize_hwaddress {
; CHECK-LABEL: @atomicrmw(
; CHECK: call void @llvm.hwasan.check.memaccess.shortgranules({{.*}}, ptr %ptr, i32 19)
; CHECK: atomicrmw add ptr %ptr, i64 1 seq_cst
; CHECK: ret void
; CHECK-LABEL: define void @atomicrmw
; CHECK-SAME: (ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP3]], ptr [[PTR]], i32 19)
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw add ptr [[PTR]], i64 1 seq_cst, align 8
; CHECK-NEXT: ret void
;
entry:
%0 = atomicrmw add ptr %ptr, i64 1 seq_cst
@ -17,10 +26,18 @@ entry:
}
define void @cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress {
; CHECK-LABEL: @cmpxchg(
; CHECK: call void @llvm.hwasan.check.memaccess.shortgranules({{.*}}, ptr %ptr, i32 19)
; CHECK: cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst
; CHECK: ret void
; CHECK-LABEL: define void @cmpxchg
; CHECK-SAME: (ptr [[PTR:%.*]], i64 [[COMPARE_TO:%.*]], i64 [[NEW_VALUE:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP2]], 1
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP3]], ptr [[PTR]], i32 19)
; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[PTR]], i64 [[COMPARE_TO]], i64 [[NEW_VALUE]] seq_cst seq_cst, align 8
; CHECK-NEXT: ret void
;
entry:
%0 = cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst

1340
llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
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File diff suppressed because it is too large Load Diff

83
llvm/test/Instrumentation/HWAddressSanitizer/RISCV/exception-lifetime.ll
View File

@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test allocas with multiple lifetime ends, as frequently seen for exception
; handling.
;
; RUN: opt -passes=hwasan -hwasan-use-after-scope -S -o - %s | FileCheck %s --check-prefix=CHECK
; RUN: opt -passes=hwasan -hwasan-use-after-scope -S -o - %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux"
@ -14,6 +15,78 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind
declare i32 @__gxx_personality_v0(...)
define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: define void @test
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk.__gxx_personality_v0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44
; CHECK-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @test to i64), [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]]
; CHECK-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP2]], 0
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = shl i64 [[TMP15]], 56
; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP18]] to ptr
; CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8
; CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[X]])
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 4
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP21]]
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[TMP22]], i32 0
; CHECK-NEXT: store i8 4, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[X]], i32 15
; CHECK-NEXT: store i8 [[TMP19]], ptr [[TMP24]], align 1
; CHECK-NEXT: invoke void @mayFail(ptr [[X_HWASAN]])
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
; CHECK: invoke.cont:
; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP26]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 0, i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: ret void
; CHECK: lpad:
; CHECK-NEXT: [[TMP28:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup
; CHECK-NEXT: [[TMP29:%.*]] = extractvalue { ptr, i32 } [[TMP28]], 0
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EXN_SLOT]], i32 19)
; CHECK-NEXT: store ptr [[TMP29]], ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: [[TMP30:%.*]] = extractvalue { ptr, i32 } [[TMP28]], 1
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EHSELECTOR_SLOT]], i32 18)
; CHECK-NEXT: store i32 [[TMP30]], ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: call void @onExcept(ptr [[X_HWASAN]])
; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP32:%.*]] = lshr i64 [[TMP31]], 4
; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP32]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP33]], i8 0, i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: br label [[EH_RESUME:%.*]]
; CHECK: eh.resume:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EXN_SLOT]], i32 3)
; CHECK-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr [[EHSELECTOR_SLOT]], i32 2)
; CHECK-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } undef, ptr [[EXN]], 0
; CHECK-NEXT: [[LPAD_VAL1:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
; CHECK-NEXT: resume { ptr, i32 } [[LPAD_VAL1]]
;
entry:
%x = alloca i32, align 8
%exn.slot = alloca ptr, align 8
@ -22,19 +95,11 @@ entry:
invoke void @mayFail(ptr %x) to label %invoke.cont unwind label %lpad
invoke.cont: ; preds = %entry
; CHECK: invoke.cont:
; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %{{.*}}, i8 0, i64 1, i1 false)
; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr {{.*}}{{.*}}%x)
; CHECK: ret void
call void @llvm.lifetime.end.p0(i64 8, ptr %x)
ret void
lpad: ; preds = %entry
; CHECK: lpad
; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %{{.*}}, i8 0, i64 1, i1 false)
; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr {{.*}}{{.*}}%x)
; CHECK: br label %eh.resume
%0 = landingpad { ptr, i32 }
cleanup

59
llvm/test/Instrumentation/HWAddressSanitizer/RISCV/use-after-scope-setjmp.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -passes=hwasan -hwasan-use-stack-safety=0 -hwasan-use-after-scope -S < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux"
@ -8,12 +9,64 @@ target triple = "riscv64-unknown-linux"
declare void @may_jump()
define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress {
; CHECK-LABEL: define dso_local noundef i1 @_Z6targetv
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 72057594037927935
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 44
; CHECK-NEXT: [[TMP6:%.*]] = or i64 ptrtoint (ptr @_Z6targetv to i64), [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr
; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP7]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = ashr i64 [[TMP0]], 56
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP8]], 12
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], -1
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP0]], 8
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], [[TMP10]]
; CHECK-NEXT: store i64 [[TMP12]], ptr @__hwasan_tls, align 8
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP1]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP13]], 1
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[BUF:%.*]] = alloca [4096 x i8], align 16
; CHECK-NEXT: [[TMP15:%.*]] = xor i64 [[TMP2]], 0
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = shl i64 [[TMP15]], 56
; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[BUF_HWASAN:%.*]] = inttoptr i64 [[TMP18]] to ptr
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 4
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP21]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP22]], i8 [[TMP19]], i64 256, i1 false)
; CHECK-NEXT: [[CALL:%.*]] = call i32 @setjmp(ptr noundef @jbuf)
; CHECK-NEXT: switch i32 [[CALL]], label [[WHILE_BODY:%.*]] [
; CHECK-NEXT: i32 1, label [[RETURN:%.*]]
; CHECK-NEXT: i32 2, label [[SW_BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: sw.bb1:
; CHECK-NEXT: br label [[RETURN]]
; CHECK: while.body:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[TMP14]], ptr @stackbuf, i32 19)
; CHECK-NEXT: store ptr [[BUF_HWASAN]], ptr @stackbuf, align 8
; CHECK-NEXT: call void @may_jump()
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ true, [[WHILE_BODY]] ], [ true, [[SW_BB1]] ], [ false, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP23]], 4
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP24]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP25]], i8 0, i64 256, i1 false)
; CHECK-NEXT: ret i1 [[RETVAL_0]]
;
entry:
%buf = alloca [4096 x i8], align 1
%call = call i32 @setjmp(ptr noundef @jbuf)
switch i32 %call, label %while.body [
i32 1, label %return
i32 2, label %sw.bb1
i32 1, label %return
i32 2, label %sw.bb1
]
sw.bb1: ; preds = %entry
@ -29,8 +82,6 @@ while.body: ; preds = %entry
call void @llvm.lifetime.end.p0(i64 4096, ptr nonnull %buf) #10
br label %return
; CHECK-LABEL: return:
; CHECK: void @llvm.memset.p0.i64({{.*}}, i8 0, i64 256, i1 false)
return: ; preds = %entry, %while.body, %sw.bb1
%retval.0 = phi i1 [ true, %while.body ], [ true, %sw.bb1 ], [ false, %entry ]
ret i1 %retval.0

32
llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=hwasan -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@ -6,9 +7,36 @@ target triple = "x86_64-unknown-linux-gnu"
declare void @use(ptr, ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK: alloca { [4 x i8], [12 x i8] }, align 16
; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 20
; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP4]], 63
; CHECK-NEXT: [[X:%.*]] = alloca { [4 x i8], [12 x i8] }, align 16
; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP5]], 57
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP8]] to ptr
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP5]] to i8
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP9]], i64 16)
; CHECK-NEXT: [[Y:%.*]] = alloca i8, i64 16, align 16
; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 1
; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[Y]] to i64
; CHECK-NEXT: [[TMP12:%.*]] = shl i64 [[TMP10]], 57
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[Y_HWASAN:%.*]] = inttoptr i64 [[TMP13]] to ptr
; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP10]] to i8
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[Y]], i8 [[TMP14]], i64 16)
; CHECK-NEXT: call void @use(ptr [[X_HWASAN]], ptr [[Y_HWASAN]])
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 0, i64 16)
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[Y]], i8 0, i64 16)
; CHECK-NEXT: ret void
;
%x = alloca i8, i64 4
; CHECK: alloca i8, i64 16, align 16
%y = alloca i8, i64 16
call void @use(ptr %x, ptr %y)
ret void

24
llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test alloca instrumentation when tags are generated by HWASan function.
;
; RUN: opt < %s -passes=hwasan -hwasan-generate-tags-with-calls -S | FileCheck %s
@ -8,12 +9,23 @@ target triple = "x86_64-unknown-linux-gnu"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[T1:[^ ]*]] = call i8 @__hwasan_generate_tag()
; CHECK: %[[A:[^ ]*]] = zext i8 %[[T1]] to i64
; CHECK: %[[B:[^ ]*]] = ptrtoint ptr %x to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[A]], 57
; CHECK: or i64 %[[B]], %[[C]]
; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @__hwasan_generate_tag()
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP1]], 57
; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP4]] to ptr
; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP1]] to i8
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP5]], i64 16)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 0, i64 16)
; CHECK-NEXT: ret void
;
entry:
%x = alloca i32, align 4

75
llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
View File

@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test alloca instrumentation.
;
; RUN: opt < %s -passes=hwasan -S | FileCheck %s --check-prefixes=CHECK,NO-UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=CHECK,UAR-TAGS
; RUN: opt < %s -passes=hwasan -S | FileCheck %s --check-prefixes=NO-UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=UAR-TAGS
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@ -9,32 +10,50 @@ target triple = "x86_64-unknown-linux-gnu"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
; CHECK: %[[A_XOR_B:[^ ]*]] = xor i64 %[[A]], %[[B]]
; CHECK: %[[BASE_TAG:[^ ]*]] = and i64 %[[A_XOR_B]], 63
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 57
; CHECK: %[[D:[^ ]*]] = or i64 %[[X1]], %[[C]]
; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to ptr
; CHECK: %[[X_TAG2:[^ ]*]] = trunc i64 %[[X_TAG]] to i8
; CHECK: call void @__hwasan_tag_memory(ptr %[[X]], i8 %[[X_TAG2]], i64 16)
; CHECK: call void @use32(ptr nonnull %[[X_HWASAN]])
; UAR-TAGS: %[[BASE_TAG_COMPL:[^ ]*]] = xor i64 %[[BASE_TAG]], 63
; UAR-TAGS: %[[X_TAG_UAR:[^ ]*]] = trunc i64 %[[BASE_TAG_COMPL]] to i8
; NO-UAR-TAGS: call void @__hwasan_tag_memory(ptr %[[X]], i8 0, i64 16)
; UAR-TAGS: call void @__hwasan_tag_memory(ptr %[[X]], i8 %[[X_TAG_UAR]], i64 16)
; CHECK: ret void
; NO-UAR-TAGS-LABEL: define void @test_alloca
; NO-UAR-TAGS-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; NO-UAR-TAGS-NEXT: entry:
; NO-UAR-TAGS-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; NO-UAR-TAGS-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; NO-UAR-TAGS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; NO-UAR-TAGS-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; NO-UAR-TAGS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; NO-UAR-TAGS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP3]], 63
; NO-UAR-TAGS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; NO-UAR-TAGS-NEXT: [[TMP4:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0
; NO-UAR-TAGS-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64
; NO-UAR-TAGS-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57
; NO-UAR-TAGS-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]]
; NO-UAR-TAGS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr
; NO-UAR-TAGS-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8
; NO-UAR-TAGS-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP8]], i64 16)
; NO-UAR-TAGS-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; NO-UAR-TAGS-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 0, i64 16)
; NO-UAR-TAGS-NEXT: ret void
;
; UAR-TAGS-LABEL: define void @test_alloca
; UAR-TAGS-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk {
; UAR-TAGS-NEXT: entry:
; UAR-TAGS-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; UAR-TAGS-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; UAR-TAGS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; UAR-TAGS-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; UAR-TAGS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; UAR-TAGS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = and i64 [[TMP3]], 63
; UAR-TAGS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; UAR-TAGS-NEXT: [[TMP4:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0
; UAR-TAGS-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[X]] to i64
; UAR-TAGS-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57
; UAR-TAGS-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]]
; UAR-TAGS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr
; UAR-TAGS-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8
; UAR-TAGS-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP8]], i64 16)
; UAR-TAGS-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; UAR-TAGS-NEXT: [[TMP9:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 63
; UAR-TAGS-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8
; UAR-TAGS-NEXT: call void @__hwasan_tag_memory(ptr [[X]], i8 [[TMP10]], i64 16)
; UAR-TAGS-NEXT: ret void
;
entry:
%x = alloca i32, align 4
call void @use32(ptr nonnull %x)

29
llvm/test/Instrumentation/HWAddressSanitizer/X86/atomic.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test basic address sanitizer instrumentation.
;
; RUN: opt < %s -passes=hwasan -S | FileCheck %s
@ -6,13 +7,17 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @atomicrmw(ptr %ptr) sanitize_hwaddress {
; CHECK-LABEL: @atomicrmw(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %ptr to i64
; CHECK-LABEL: define void @atomicrmw
; CHECK-SAME: (ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[PTR]] to i64
; CHECK-NEXT: call void @__hwasan_store8(i64 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr [[PTR]], i64 1 seq_cst, align 8
; CHECK-NEXT: ret void
;
; CHECK: call void @__hwasan_store8(i64 %[[A]])
; CHECK: atomicrmw add ptr %ptr, i64 1 seq_cst
; CHECK: ret void
entry:
%0 = atomicrmw add ptr %ptr, i64 1 seq_cst
@ -20,13 +25,17 @@ entry:
}
define void @cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress {
; CHECK-LABEL: @cmpxchg(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %ptr to i64
; CHECK-LABEL: define void @cmpxchg
; CHECK-SAME: (ptr [[PTR:%.*]], i64 [[COMPARE_TO:%.*]], i64 [[NEW_VALUE:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[PTR]] to i64
; CHECK-NEXT: call void @__hwasan_store8(i64 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[PTR]], i64 [[COMPARE_TO]], i64 [[NEW_VALUE]] seq_cst seq_cst, align 8
; CHECK-NEXT: ret void
;
; CHECK: call void @__hwasan_store8(i64 %[[A]])
; CHECK: cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst
; CHECK: ret void
entry:
%0 = cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst

125
llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
View File

@ -1,22 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test basic address sanitizer instrumentation.
; Generic code is covered by ../basic.ll, only the x86_64 specific code is
; tested here.
;
; RUN: opt < %s -passes=hwasan -hwasan-recover=0 -S | FileCheck %s --check-prefixes=CHECK,ABORT
; RUN: opt < %s -passes=hwasan -hwasan-recover=1 -S | FileCheck %s --check-prefixes=CHECK,RECOVER
; RUN: opt < %s -passes=hwasan -hwasan-recover=0 -S | FileCheck %s --check-prefixes=ABORT
; RUN: opt < %s -passes=hwasan -hwasan-recover=1 -S | FileCheck %s --check-prefixes=RECOVER
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define i8 @test_load8(ptr %a) sanitize_hwaddress {
; CHECK-LABEL: @test_load8(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64
; ABORT-LABEL: define i8 @test_load8
; ABORT-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; ABORT-NEXT: entry:
; ABORT-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ABORT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; ABORT-NEXT: call void @__hwasan_load1(i64 [[TMP0]])
; ABORT-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4
; ABORT-NEXT: ret i8 [[B]]
;
; RECOVER-LABEL: define i8 @test_load8
; RECOVER-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; RECOVER-NEXT: entry:
; RECOVER-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; RECOVER-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; RECOVER-NEXT: call void @__hwasan_load1_noabort(i64 [[TMP0]])
; RECOVER-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4
; RECOVER-NEXT: ret i8 [[B]]
;
; ABORT: call void @__hwasan_load1(i64 %[[A]])
; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]])
; CHECK: %[[G:[^ ]*]] = load i8, ptr %a, align 4
; CHECK: ret i8 %[[G]]
entry:
%b = load i8, ptr %a, align 4
@ -24,14 +37,26 @@ entry:
}
define i40 @test_load40(ptr %a) sanitize_hwaddress {
; CHECK-LABEL: @test_load40(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64
; ABORT-LABEL: define i40 @test_load40
; ABORT-SAME: (ptr [[A:%.*]]) #[[ATTR0]] {
; ABORT-NEXT: entry:
; ABORT-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ABORT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; ABORT-NEXT: call void @__hwasan_loadN(i64 [[TMP0]], i64 5)
; ABORT-NEXT: [[B:%.*]] = load i40, ptr [[A]], align 4
; ABORT-NEXT: ret i40 [[B]]
;
; RECOVER-LABEL: define i40 @test_load40
; RECOVER-SAME: (ptr [[A:%.*]]) #[[ATTR0]] {
; RECOVER-NEXT: entry:
; RECOVER-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; RECOVER-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; RECOVER-NEXT: call void @__hwasan_loadN_noabort(i64 [[TMP0]], i64 5)
; RECOVER-NEXT: [[B:%.*]] = load i40, ptr [[A]], align 4
; RECOVER-NEXT: ret i40 [[B]]
;
; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5)
; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5)
; CHECK: %[[B:[^ ]*]] = load i40, ptr %a
; CHECK: ret i40 %[[B]]
entry:
%b = load i40, ptr %a, align 4
@ -39,14 +64,26 @@ entry:
}
define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress {
; CHECK-LABEL: @test_store8(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64
; ABORT-LABEL: define void @test_store8
; ABORT-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] {
; ABORT-NEXT: entry:
; ABORT-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ABORT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; ABORT-NEXT: call void @__hwasan_store1(i64 [[TMP0]])
; ABORT-NEXT: store i8 [[B]], ptr [[A]], align 4
; ABORT-NEXT: ret void
;
; RECOVER-LABEL: define void @test_store8
; RECOVER-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] {
; RECOVER-NEXT: entry:
; RECOVER-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; RECOVER-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; RECOVER-NEXT: call void @__hwasan_store1_noabort(i64 [[TMP0]])
; RECOVER-NEXT: store i8 [[B]], ptr [[A]], align 4
; RECOVER-NEXT: ret void
;
; ABORT: call void @__hwasan_store1(i64 %[[A]])
; RECOVER: call void @__hwasan_store1_noabort(i64 %[[A]])
; CHECK: store i8 %b, ptr %a, align 4
; CHECK: ret void
entry:
store i8 %b, ptr %a, align 4
@ -54,14 +91,26 @@ entry:
}
define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress {
; CHECK-LABEL: @test_store40(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64
; ABORT-LABEL: define void @test_store40
; ABORT-SAME: (ptr [[A:%.*]], i40 [[B:%.*]]) #[[ATTR0]] {
; ABORT-NEXT: entry:
; ABORT-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ABORT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; ABORT-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 5)
; ABORT-NEXT: store i40 [[B]], ptr [[A]], align 4
; ABORT-NEXT: ret void
;
; RECOVER-LABEL: define void @test_store40
; RECOVER-SAME: (ptr [[A:%.*]], i40 [[B:%.*]]) #[[ATTR0]] {
; RECOVER-NEXT: entry:
; RECOVER-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; RECOVER-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; RECOVER-NEXT: call void @__hwasan_storeN_noabort(i64 [[TMP0]], i64 5)
; RECOVER-NEXT: store i40 [[B]], ptr [[A]], align 4
; RECOVER-NEXT: ret void
;
; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5)
; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5)
; CHECK: store i40 %b, ptr %a
; CHECK: ret void
entry:
store i40 %b, ptr %a, align 4
@ -69,14 +118,26 @@ entry:
}
define void @test_store_unaligned(ptr %a, i64 %b) sanitize_hwaddress {
; CHECK-LABEL: @test_store_unaligned(
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64
; ABORT-LABEL: define void @test_store_unaligned
; ABORT-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
; ABORT-NEXT: entry:
; ABORT-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ABORT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; ABORT-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 8)
; ABORT-NEXT: store i64 [[B]], ptr [[A]], align 4
; ABORT-NEXT: ret void
;
; RECOVER-LABEL: define void @test_store_unaligned
; RECOVER-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
; RECOVER-NEXT: entry:
; RECOVER-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; RECOVER-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64
; RECOVER-NEXT: call void @__hwasan_storeN_noabort(i64 [[TMP0]], i64 8)
; RECOVER-NEXT: store i64 [[B]], ptr [[A]], align 4
; RECOVER-NEXT: ret void
;
; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 8)
; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 8)
; CHECK: store i64 %b, ptr %a, align 4
; CHECK: ret void
entry:
store i64 %b, ptr %a, align 4

58
llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=hwasan -S | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@ -6,9 +7,62 @@ target triple = "aarch64--linux-android"
declare void @use(ptr, ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK: alloca { [4 x i8], [12 x i8] }, align 16
; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3
; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44
; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56
; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12
; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]
; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 8
; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1
; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[X:%.*]] = alloca { [4 x i8], [12 x i8] }, align 16
; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP4]], 0
; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP18]], 56
; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[TMP19]], [[TMP20]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr
; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP18]] to i8
; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP23]], 4
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP24]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP25]], i8 [[TMP22]], i64 1, i1 false)
; CHECK-NEXT: [[Y:%.*]] = alloca i8, i64 16, align 16
; CHECK-NEXT: [[TMP26:%.*]] = xor i64 [[TMP4]], 128
; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr [[Y]] to i64
; CHECK-NEXT: [[TMP28:%.*]] = shl i64 [[TMP26]], 56
; CHECK-NEXT: [[TMP29:%.*]] = or i64 [[TMP27]], [[TMP28]]
; CHECK-NEXT: [[Y_HWASAN:%.*]] = inttoptr i64 [[TMP29]] to ptr
; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP26]] to i8
; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[Y]] to i64
; CHECK-NEXT: [[TMP32:%.*]] = lshr i64 [[TMP31]], 4
; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP32]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP33]], i8 [[TMP30]], i64 1, i1 false)
; CHECK-NEXT: call void @use(ptr [[X_HWASAN]], ptr [[Y_HWASAN]])
; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4
; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP35]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP36]], i8 0, i64 1, i1 false)
; CHECK-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[Y]] to i64
; CHECK-NEXT: [[TMP38:%.*]] = lshr i64 [[TMP37]], 4
; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP38]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP39]], i8 0, i64 1, i1 false)
; CHECK-NEXT: ret void
;
%x = alloca i8, i64 4
; CHECK: alloca i8, i64 16, align 16
%y = alloca i8, i64 16
call void @use(ptr %x, ptr %y)
ret void

49
llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test alloca instrumentation when tags are generated by HWASan function.
;
; RUN: opt < %s -passes=hwasan -hwasan-generate-tags-with-calls -S | FileCheck %s
@ -8,12 +9,48 @@ target triple = "aarch64--linux-android"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[T1:[^ ]*]] = call i8 @__hwasan_generate_tag()
; CHECK: %[[A:[^ ]*]] = zext i8 %[[T1]] to i64
; CHECK: %[[B:[^ ]*]] = ptrtoint ptr %x to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[A]], 56
; CHECK: or i64 %[[B]], %[[C]]
; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]]
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP17:%.*]] = call i8 @__hwasan_generate_tag()
; CHECK-NEXT: [[TMP18:%.*]] = zext i8 [[TMP17]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP18]], 56
; CHECK-NEXT: [[TMP21:%.*]] = or i64 [[TMP19]], [[TMP20]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP21]] to ptr
; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP18]] to i8
; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP23]], 4
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP24]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP25]], i8 [[TMP22]], i64 1, i1 false)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 4
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP27]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP28]], i8 0, i64 1, i1 false)
; CHECK-NEXT: ret void
;
entry:
%x = alloca i32, align 4

137
llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
View File

@ -1,8 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test alloca instrumentation.
;
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,NO-UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=CHECK,ZERO-BASED-SHADOW,NO-UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,UAR-TAGS
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -S | FileCheck %s --check-prefixes=DYNAMIC-SHADOW
; RUN: opt < %s -passes=hwasan -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=ZERO-BASED-SHADOW
; RUN: opt < %s -passes=hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=DYNAMIC-SHADOW-UAR-TAGS
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android10000"
@ -10,44 +11,98 @@ target triple = "aarch64--linux-android10000"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress !dbg !15 {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56
; CHECK: %[[D:[^ ]*]] = or i64 %[[X1]], %[[C]]
; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to ptr
; CHECK: %[[X_TAG2:[^ ]*]] = trunc i64 %[[X_TAG]] to i8
; CHECK: %[[E:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[F:[^ ]*]] = lshr i64 %[[E]], 4
; DYNAMIC-SHADOW: %[[X_SHADOW:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %[[F]]
; ZERO-BASED-SHADOW: %[[X_SHADOW:[^ ]*]] = inttoptr i64 %[[F]] to ptr
; CHECK: %[[X_SHADOW_GEP:[^ ]*]] = getelementptr i8, ptr %[[X_SHADOW]], i32 0
; CHECK: store i8 4, ptr %[[X_SHADOW_GEP]]
; CHECK: %[[X_I8_GEP:[^ ]*]] = getelementptr i8, ptr %[[X]], i32 15
; CHECK: store i8 %[[X_TAG2]], ptr %[[X_I8_GEP]]
; CHECK: call void @llvm.dbg.value(
; CHECK-SAME: metadata !DIArgList(ptr %[[X]], ptr %[[X]])
; CHECK-SAME: metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0,
; CHECK: call void @use32(ptr nonnull %[[X_HWASAN]])
; UAR-TAGS: %[[BASE_TAG_COMPL:[^ ]*]] = xor i64 %[[BASE_TAG]], 255
; UAR-TAGS: %[[X_TAG_UAR:[^ ]*]] = trunc i64 %[[BASE_TAG_COMPL]] to i8
; CHECK: %[[E2:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[F2:[^ ]*]] = lshr i64 %[[E2]], 4
; DYNAMIC-SHADOW: %[[X_SHADOW2:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %[[F2]]
; ZERO-BASED-SHADOW: %[[X_SHADOW2:[^ ]*]] = inttoptr i64 %[[F2]] to ptr
; NO-UAR-TAGS: call void @llvm.memset.p0.i64(ptr align 1 %[[X_SHADOW2]], i8 0, i64 1, i1 false)
; UAR-TAGS: call void @llvm.memset.p0.i64(ptr align 1 %[[X_SHADOW2]], i8 %[[X_TAG_UAR]], i64 1, i1 false)
; CHECK: ret void
; DYNAMIC-SHADOW-LABEL: define void @test_alloca
; DYNAMIC-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; DYNAMIC-SHADOW-NEXT: entry:
; DYNAMIC-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; DYNAMIC-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; DYNAMIC-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; DYNAMIC-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; DYNAMIC-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; DYNAMIC-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; DYNAMIC-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 4, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP9]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 4, ptr [[TMP11]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: store i8 [[TMP7]], ptr [[TMP12]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; DYNAMIC-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14:![0-9]+]]
; DYNAMIC-SHADOW-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP13]], 4, !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP14]], !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP15]], i8 0, i64 1, i1 false), !dbg [[DBG14]]
; DYNAMIC-SHADOW-NEXT: ret void, !dbg [[DBG14]]
;
; ZERO-BASED-SHADOW-LABEL: define void @test_alloca
; ZERO-BASED-SHADOW-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; ZERO-BASED-SHADOW-NEXT: entry:
; ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; ZERO-BASED-SHADOW-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; ZERO-BASED-SHADOW-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; ZERO-BASED-SHADOW-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; ZERO-BASED-SHADOW-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; ZERO-BASED-SHADOW-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; ZERO-BASED-SHADOW-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]], !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 4, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 4, ptr [[TMP11]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: store i8 [[TMP7]], ptr [[TMP12]], align 1, !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; ZERO-BASED-SHADOW-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14:![0-9]+]]
; ZERO-BASED-SHADOW-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP13]], 4, !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP15]], i8 0, i64 1, i1 false), !dbg [[DBG14]]
; ZERO-BASED-SHADOW-NEXT: ret void, !dbg [[DBG14]]
;
; DYNAMIC-SHADOW-UAR-TAGS-LABEL: define void @test_alloca
; DYNAMIC-SHADOW-UAR-TAGS-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__hwasan_personality_thunk !dbg [[DBG7:![0-9]+]] {
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: entry:
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0, !dbg [[DBG10:![0-9]+]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 4, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP9]], !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: store i8 4, ptr [[TMP11]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[X]], i32 15, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: store i8 [[TMP7]], ptr [[TMP12]], align 1, !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, DW_OP_plus, DW_OP_deref)), !dbg [[DBG10]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: call void @use32(ptr nonnull [[X_HWASAN]]), !dbg [[DBG13:![0-9]+]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP13:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 255, !dbg [[DBG14:![0-9]+]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8, !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[X]] to i64, !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP15]], 4, !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[DOTHWASAN_SHADOW]], i64 [[TMP16]], !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP17]], i8 [[TMP14]], i64 1, i1 false), !dbg [[DBG14]]
; DYNAMIC-SHADOW-UAR-TAGS-NEXT: ret void, !dbg [[DBG14]]
;
entry:
%x = alloca i32, align 4
call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21

25
llvm/test/Instrumentation/HWAddressSanitizer/atomic.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test basic address sanitizer instrumentation.
;
; RUN: opt < %s -passes=hwasan -S | FileCheck %s
@ -6,10 +7,14 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android"
define void @atomicrmw(ptr %ptr) sanitize_hwaddress {
; CHECK-LABEL: @atomicrmw(
; CHECK: call void @llvm.hwasan.check.memaccess({{.*}}, ptr %ptr, i32 19)
; CHECK: atomicrmw add ptr %ptr, i64 1 seq_cst
; CHECK: ret void
; CHECK-LABEL: define void @atomicrmw
; CHECK-SAME: (ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[DOTHWASAN_SHADOW]], ptr [[PTR]], i32 19)
; CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR]], i64 1 seq_cst, align 8
; CHECK-NEXT: ret void
;
entry:
%0 = atomicrmw add ptr %ptr, i64 1 seq_cst
@ -17,10 +22,14 @@ entry:
}
define void @cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress {
; CHECK-LABEL: @cmpxchg(
; CHECK: call void @llvm.hwasan.check.memaccess({{.*}}, ptr %ptr, i32 19)
; CHECK: cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst
; CHECK: ret void
; CHECK-LABEL: define void @cmpxchg
; CHECK-SAME: (ptr [[PTR:%.*]], i64 [[COMPARE_TO:%.*]], i64 [[NEW_VALUE:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[DOTHWASAN_SHADOW]], ptr [[PTR]], i32 19)
; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[PTR]], i64 [[COMPARE_TO]], i64 [[NEW_VALUE]] seq_cst seq_cst, align 8
; CHECK-NEXT: ret void
;
entry:
%0 = cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst

10
llvm/test/Instrumentation/HWAddressSanitizer/basic-compat.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test that the old outlined check is used with old API levels.
; RUN: opt < %s -passes=hwasan -S | FileCheck %s
@ -6,8 +7,13 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android"
define i8 @test_load8(ptr %a) sanitize_hwaddress {
; CHECK-LABEL: @test_load8(
; CHECK: call void @llvm.hwasan.check.memaccess(ptr {{.*}}, ptr {{.*}}, i32 0)
; CHECK-LABEL: define i8 @test_load8
; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow)
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 0)
; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4
; CHECK-NEXT: ret i8 [[B]]
;
%b = load i8, ptr %a, align 4
ret i8 %b
}

1340
llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
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File diff suppressed because it is too large Load Diff

84
llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll
View File

@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test allocas with multiple lifetime ends, as frequently seen for exception
; handling.
;
; RUN: opt -passes=hwasan -hwasan-use-after-scope -S -o - %s | FileCheck %s --check-prefix=CHECK
; RUN: opt -passes=hwasan -hwasan-use-after-scope -S -o - %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android"
@ -14,6 +15,79 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind
declare i32 @__gxx_personality_v0(...)
define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: define void @test
; CHECK-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]]
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP3]], 0
; CHECK-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = shl i64 [[TMP17]], 56
; CHECK-NEXT: [[TMP20:%.*]] = or i64 [[TMP18]], [[TMP19]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP20]] to ptr
; CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8
; CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[X]])
; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP17]] to i8
; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 4
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP23]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP24]], i8 [[TMP21]], i64 1, i1 false)
; CHECK-NEXT: invoke void @mayFail(ptr [[X_HWASAN]])
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
; CHECK: invoke.cont:
; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP26]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 0, i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: ret void
; CHECK: lpad:
; CHECK-NEXT: [[TMP28:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup
; CHECK-NEXT: [[TMP29:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]])
; CHECK-NEXT: call void @__hwasan_handle_vfork(i64 [[TMP29]])
; CHECK-NEXT: [[TMP30:%.*]] = extractvalue { ptr, i32 } [[TMP28]], 0
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EXN_SLOT]], i32 19)
; CHECK-NEXT: store ptr [[TMP30]], ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: [[TMP31:%.*]] = extractvalue { ptr, i32 } [[TMP28]], 1
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EHSELECTOR_SLOT]], i32 18)
; CHECK-NEXT: store i32 [[TMP31]], ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: call void @onExcept(ptr [[X_HWASAN]])
; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4
; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP33]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false)
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[X]])
; CHECK-NEXT: br label [[EH_RESUME:%.*]]
; CHECK: eh.resume:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EXN_SLOT]], i32 3)
; CHECK-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr [[EHSELECTOR_SLOT]], i32 2)
; CHECK-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
; CHECK-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } undef, ptr [[EXN]], 0
; CHECK-NEXT: [[LPAD_VAL1:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
; CHECK-NEXT: resume { ptr, i32 } [[LPAD_VAL1]]
;
entry:
%x = alloca i32, align 8
%exn.slot = alloca ptr, align 8
@ -22,19 +96,11 @@ entry:
invoke void @mayFail(ptr %x) to label %invoke.cont unwind label %lpad
invoke.cont: ; preds = %entry
; CHECK: invoke.cont:
; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %{{.*}}, i8 0, i64 1, i1 false)
; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr {{.*}}{{.*}}%x)
; CHECK: ret void
call void @llvm.lifetime.end.p0(i64 8, ptr %x)
ret void
lpad: ; preds = %entry
; CHECK: lpad
; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %{{.*}}, i8 0, i64 1, i1 false)
; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr {{.*}}{{.*}}%x)
; CHECK: br label %eh.resume
%0 = landingpad { ptr, i32 }
cleanup

40
llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Test kernel hwasan instrumentation for alloca.
;
; RUN: opt < %s -passes=hwasan -hwasan-kernel=1 -S | FileCheck %s
@ -8,19 +9,34 @@ target triple = "aarch64--linux-android"
declare void @use32(ptr)
define void @test_alloca() sanitize_hwaddress {
; CHECK-LABEL: @test_alloca(
; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64
; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20
; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]]
; CHECK-LABEL: define void @test_alloca
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null)
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 20
; CHECK-NEXT: [[HWASAN_STACK_BASE_TAG:%.*]] = xor i64 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 16
; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[HWASAN_STACK_BASE_TAG]], 0
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 56
; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 72057594037927935
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8
; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = lshr i64 [[TMP9]], 4
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP11]], i8 [[TMP8]], i64 1, i1 false)
; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])
; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[X]] to i64
; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP12]], 4
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP14]], i8 0, i64 1, i1 false)
; CHECK-NEXT: ret void
;
; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16
; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0
; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64
; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56
; CHECK: %[[D:[^ ]*]] = or i64 %[[C]], 72057594037927935
; CHECK: %[[E:[^ ]*]] = and i64 %[[X1]], %[[D]]
; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[E]] to ptr
entry:
%x = alloca i32, align 4

61
llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -passes=hwasan -hwasan-use-stack-safety=0 -hwasan-use-after-scope -S < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-android29"
@ -8,12 +9,66 @@ target triple = "aarch64-unknown-linux-android29"
declare void @may_jump()
define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress {
; CHECK-LABEL: define dso_local noundef i1 @_Z6targetv
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.thread.pointer()
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 44
; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: store i64 [[TMP8]], ptr [[TMP9]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = ashr i64 [[TMP2]], 56
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i64 [[TMP10]], 12
; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], -1
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP2]], 8
; CHECK-NEXT: [[TMP14:%.*]] = and i64 [[TMP13]], [[TMP12]]
; CHECK-NEXT: store i64 [[TMP14]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP15:%.*]] = or i64 [[TMP2]], 4294967295
; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP15]], 1
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr
; CHECK-NEXT: [[BUF:%.*]] = alloca [4096 x i8], align 16
; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP3]], 0
; CHECK-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = shl i64 [[TMP17]], 56
; CHECK-NEXT: [[TMP20:%.*]] = or i64 [[TMP18]], [[TMP19]]
; CHECK-NEXT: [[BUF_HWASAN:%.*]] = inttoptr i64 [[TMP20]] to ptr
; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP17]] to i8
; CHECK-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 4
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP23]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP24]], i8 [[TMP21]], i64 256, i1 false)
; CHECK-NEXT: [[CALL:%.*]] = call i32 @setjmp(ptr noundef @jbuf)
; CHECK-NEXT: switch i32 [[CALL]], label [[WHILE_BODY:%.*]] [
; CHECK-NEXT: i32 1, label [[RETURN:%.*]]
; CHECK-NEXT: i32 2, label [[SW_BB1:%.*]]
; CHECK-NEXT: ]
; CHECK: sw.bb1:
; CHECK-NEXT: br label [[RETURN]]
; CHECK: while.body:
; CHECK-NEXT: call void @llvm.hwasan.check.memaccess(ptr [[TMP16]], ptr @stackbuf, i32 19)
; CHECK-NEXT: store ptr [[BUF_HWASAN]], ptr @stackbuf, align 8
; CHECK-NEXT: call void @may_jump()
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ true, [[WHILE_BODY]] ], [ true, [[SW_BB1]] ], [ false, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[BUF]] to i64
; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP26]]
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 0, i64 256, i1 false)
; CHECK-NEXT: ret i1 [[RETVAL_0]]
;
entry:
%buf = alloca [4096 x i8], align 1
%call = call i32 @setjmp(ptr noundef @jbuf)
switch i32 %call, label %while.body [
i32 1, label %return
i32 2, label %sw.bb1
i32 1, label %return
i32 2, label %sw.bb1
]
sw.bb1: ; preds = %entry
@ -29,8 +84,6 @@ while.body: ; preds = %entry
call void @llvm.lifetime.end.p0(i64 4096, ptr nonnull %buf) #10
br label %return
; CHECK-LABEL: return:
; CHECK: void @llvm.memset.p0.i64({{.*}}, i8 0, i64 256, i1 false)
return: ; preds = %entry, %while.body, %sw.bb1
%retval.0 = phi i1 [ true, %while.body ], [ true, %sw.bb1 ], [ false, %entry ]
ret i1 %retval.0