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[ARM] Implement isTruncateFree

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Implement the isTruncateFree hooks, lifted from AArch64, that are
used by TargetTransformInfo. This allows simplifycfg to reduce the
test case into a single basic block.

Differential Revision: https://reviews.llvm.org/D37516

llvm-svn: 313533
This commit is contained in:
Sam Parker 2017-09-18 14:28:51 +00:00
parent 00161c9961
commit 71efbe4c68
3 changed files with 47 additions and 1 deletions
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20
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -12179,6 +12179,26 @@ EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
return MVT::Other;
}
// 64-bit integers are split into their high and low parts and held in two
// different registers, so the trunc is free since the low register can just
// be used.
bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
return false;
unsigned NumBits1 = SrcTy->getPrimitiveSizeInBits();
unsigned NumBits2 = DstTy->getPrimitiveSizeInBits();
return NumBits1 > NumBits2;
}
bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() ||
!DstVT.isInteger())
return false;
unsigned NumBits1 = SrcVT.getSizeInBits();
unsigned NumBits2 = DstVT.getSizeInBits();
return NumBits1 > NumBits2;
}
bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
if (Val.getOpcode() != ISD::LOAD)
return false;

3
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -308,7 +308,8 @@ class InstrItineraryData;
bool MemcpyStrSrc,
MachineFunction &MF) const override;
using TargetLowering::isZExtFree;
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
bool isZExtFree(SDValue Val, EVT VT2) const override;
bool isVectorLoadExtDesirable(SDValue ExtVal) const override;

25
llvm/test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll Normal file
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@ -0,0 +1,25 @@
;RUN: opt -S -simplifycfg -mtriple=arm < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
; CHECK-LABEL: select_trunc_i64
; CHECK-NOT: br
; CHECK: select
; CHECK: select
define arm_aapcscc i32 @select_trunc_i64(i32 %a, i32 %b) {
entry:
%conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64
%add = add nsw i64 %conv1, %conv
%cmp = icmp sgt i64 %add, 2147483647
br i1 %cmp, label %cond.end7, label %cond.false
cond.false: ; preds = %entry
%0 = icmp sgt i64 %add, -2147483648
%cond = select i1 %0, i64 %add, i64 -2147483648
%extract.t = trunc i64 %cond to i32
br label %cond.end7
cond.end7: ; preds = %cond.false, %entry
%cond8.off0 = phi i32 [ 2147483647, %entry ], [ %extract.t, %cond.false ]
ret i32 %cond8.off0
}