Capestone: Add missing bc0f-bc3f for Mips

2024-11-26 23:21:11 +00:00 · 2021-11-30 23:16:53 +08:00 · 2021-11-30 23:16:53 +08:00 · 7599468143
commit 7599468143
parent 71b8895149
5 changed files with 150 additions and 3 deletions
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@ -231,6 +231,17 @@ class SWXC1_FT<string opstr, RegisterOperand DRC,
  let AddedComplexity = 20;
 }

+class BC0F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
+  InstSE<(outs), (ins opnd:$offset),
+         !strconcat(opstr, "\t$offset"),
+         [], Itin,
+         FrmFI, opstr> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = 1;
+  let Defs = [AT];
+}
+
 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
              SDPatternOperator Op = null_frag> :
  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
@ -244,6 +255,32 @@ class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
  let hasFCCRegOperand = 1;
 }

+class BC2F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+              SDPatternOperator Op = null_frag> :
+  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
+         !strconcat(opstr, "\t$fcc, $offset"),
+         [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
+         FrmFI, opstr>, HARDFLOAT {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = 1;
+  let Defs = [AT];
+  let hasFCCRegOperand = 1;
+}
+
+class BC3F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+              SDPatternOperator Op = null_frag> :
+  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
+         !strconcat(opstr, "\t$fcc, $offset"),
+         [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
+         FrmFI, opstr>, HARDFLOAT {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = 1;
+  let Defs = [AT];
+  let hasFCCRegOperand = 1;
+}
+
 class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
         !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
@ -255,6 +292,28 @@ class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
  let hasFCCRegOperand = 1;
 }

+class BC2XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
+  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
+         !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
+         FrmFI, opstr>, HARDFLOAT {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = 1;
+  let Defs = [AT];
+  let hasFCCRegOperand = 1;
+}
+
+class BC3XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
+  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
+         !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
+         FrmFI, opstr>, HARDFLOAT {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasDelaySlot = 1;
+  let Defs = [AT];
+  let hasFCCRegOperand = 1;
+}
+
 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
              SDPatternOperator OpNode = null_frag>  :
  InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
@ -727,6 +786,10 @@ def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
 def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;

 let AdditionalPredicates = [NotInMicroMips] in {
+  def BC0F : MMRel, BC0F_FT<"bc0f", brtarget, II_BC0F>,
+           BC0F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+  def BC0T : MMRel, BC0F_FT<"bc0t", brtarget, II_BC0F>,
+           BC0F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
  def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
             BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
  def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
@ -735,6 +798,22 @@ let AdditionalPredicates = [NotInMicroMips] in {
             BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
  def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
              BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
+  def BC2F : MMRel, BC2F_FT<"bc2f", brtarget, II_BC2F, MIPS_BRANCH_F>,
+             BC2F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+  def BC2FL : MMRel, BC2XL_FT<"bc2fl", brtarget, II_BC2FL>,
+              BC2F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
+  def BC2T : MMRel, BC2F_FT<"bc2t", brtarget, II_BC2T, MIPS_BRANCH_T>,
+             BC2F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
+  def BC2TL : MMRel, BC2XL_FT<"bc2tl", brtarget, II_BC2TL>,
+              BC2F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
+  def BC3F : MMRel, BC3F_FT<"bc3f", brtarget, II_BC3F, MIPS_BRANCH_F>,
+             BC3F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+  def BC3FL : MMRel, BC3XL_FT<"bc3fl", brtarget, II_BC3FL>,
+              BC3F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
+  def BC3T : MMRel, BC3F_FT<"bc3t", brtarget, II_BC3T, MIPS_BRANCH_T>,
+             BC3F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
+  def BC3TL : MMRel, BC3XL_FT<"bc3tl", brtarget, II_BC3TL>,
+              BC3F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;

 /// Floating Point Compare
  def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
@ -930,6 +1009,16 @@ let AdditionalPredicates = [NotInMicroMips] in {
         HARDFLOAT;
  defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
         HARDFLOAT;
+// bc1 alias shares the same property, so reuse
+  defm : BC1_ALIASES<BC2T, "bc2t", BC2F, "bc2f">, ISA_MIPS1_NOT_32R6_64R6,
+         HARDFLOAT;
+  defm : BC1_ALIASES<BC2TL, "bc2tl", BC2FL, "bc2fl">, ISA_MIPS2_NOT_32R6_64R6,
+         HARDFLOAT;
+
+  defm : BC1_ALIASES<BC3T, "bc3t", BC3F, "bc3f">, ISA_MIPS1_NOT_32R6_64R6,
+         HARDFLOAT;
+  defm : BC1_ALIASES<BC3TL, "bc3tl", BC3FL, "bc3fl">, ISA_MIPS2_NOT_32R6_64R6,
+         HARDFLOAT;
 }
 //===----------------------------------------------------------------------===//
 // Floating Point Patterns
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@ -779,6 +779,20 @@ class SWXC1_FM<bits<6> funct> : StdArch {
  let Inst{5-0}   = funct;
 }

+class BC0F_FM<bit HasDelaySlot, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x10;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = 0x0;
+  let Inst{17} = HasDelaySlot;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class BC1F_FM<bit nd, bit tf> : StdArch {
  bits<3>  fcc;
  bits<16> offset;
@ -793,6 +807,34 @@ class BC1F_FM<bit nd, bit tf> : StdArch {
  let Inst{15-0} = offset;
 }

+class BC2F_FM<bit nd, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x12;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = fcc;
+  let Inst{17} = nd;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
+class BC3F_FM<bit nd, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x13;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = fcc;
+  let Inst{17} = nd;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class CEQS_FM<bits<5> fmt> : StdArch {
  bits<5> fs;
  bits<5> ft;
--- a/llvm/lib/Target/Mips/MipsSchedule.td
+++ b/llvm/lib/Target/Mips/MipsSchedule.td
@ -40,10 +40,20 @@ def II_BADDU            : InstrItinClass;
 def II_BBIT             : InstrItinClass; // bbit[01], bbit[01]32
 def II_BALC             : InstrItinClass;
 def II_BC               : InstrItinClass;
+def II_BC0F             : InstrItinClass;
+def II_BC0T             : InstrItinClass;
 def II_BC1F             : InstrItinClass;
 def II_BC1FL            : InstrItinClass;
 def II_BC1T             : InstrItinClass;
 def II_BC1TL            : InstrItinClass;
+def II_BC2F             : InstrItinClass;
+def II_BC2FL            : InstrItinClass;
+def II_BC2T             : InstrItinClass;
+def II_BC2TL            : InstrItinClass;
+def II_BC3F             : InstrItinClass;
+def II_BC3FL            : InstrItinClass;
+def II_BC3T             : InstrItinClass;
+def II_BC3TL            : InstrItinClass;
 def II_BC1CCZ           : InstrItinClass;
 def II_BC2CCZ           : InstrItinClass;
 def II_BCC              : InstrItinClass; // beq and bne
@ -516,6 +526,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
  InstrItinData<II_BC              , [InstrStage<1,  [ALU]>]>,
  InstrItinData<II_BC1F            , [InstrStage<1,  [ALU]>]>,
  InstrItinData<II_BC1FL           , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_BC0F            , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_BC0T           , [InstrStage<1,  [ALU]>]>,
  InstrItinData<II_BC1T            , [InstrStage<1,  [ALU]>]>,
  InstrItinData<II_BC1TL           , [InstrStage<1,  [ALU]>]>,
  InstrItinData<II_BC1CCZ          , [InstrStage<1,  [ALU]>]>,
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@ -796,8 +796,10 @@ def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
 // ---------------------------------
 //
 // c.<cc>.[ds], bc1[tf], bc1[tf]l
-def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_D32, FCMP_D64, FCMP_S32, BC1F,
-                                    BC1T, BC1FL, BC1TL)>;
+def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_D32, FCMP_D64, FCMP_S32, BC0F, BC0T, BC1F,
+                                    BC1T, BC1FL, BC1TL, BC2F,
+                                    BC2T, BC2FL, BC2TL, BC3F,
+                                    BC3T, BC3FL, BC3TL)>;

 def : InstRW<[GenericWriteFPUCmp], (instregex "C_[A-Z]+_(S|D32|D64)$")>;

--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@ -570,7 +570,9 @@ def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_U_[BHW]$")>;
 def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_S_[BHWD]$")>;

 // bc1[ft], cfc1, mfc1, mfhc1, movf, movt
-def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1,
+def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC0F, BC0T, BC1F, BC1FL, BC1T, BC1TL, BC2F,
+                                    BC2T, BC2FL, BC2TL, BC3F,
+                                    BC3T, BC3FL, BC3TL, CFC1,
                                        MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64,
                                        MOVF_I, MOVT_I, ExtractElementF64,
                                        ExtractElementF64_64)>;