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Recommit "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."
This recommits 2c51bef76c
.
I've fixed the broken check line from when I renamed the test function.
Original commit message:
This builds on D94142 where scalable vectors are allowed in structs.
I did have to fix one scalable vector issue in the vector type
creation for these intrinsics where we used getVectorNumElements
instead of ElementCount.
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@ -6602,7 +6602,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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EVT OverflowVT = MVT::i1;
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if (ResultVT.isVector())
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OverflowVT = EVT::getVectorVT(
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*Context, OverflowVT, ResultVT.getVectorNumElements());
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*Context, OverflowVT, ResultVT.getVectorElementCount());
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SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT);
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setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
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23
llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
Normal file
23
llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
Normal file
@ -0,0 +1,23 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
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declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
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define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
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; CHECK-LABEL: saddo_nvx2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
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; CHECK-NEXT: vmslt.vx v25, v17, zero
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; CHECK-NEXT: vadd.vv v26, v16, v17
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; CHECK-NEXT: vmslt.vv v27, v26, v16
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; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
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; CHECK-NEXT: vmxor.mm v0, v25, v27
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; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
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; CHECK-NEXT: vmerge.vim v16, v26, 0, v0
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; CHECK-NEXT: ret
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%a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
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%b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
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%c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
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%d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
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ret <vscale x 2 x i32> %d
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}
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