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[RISCV] Switch vwsll.v* instructions to use the VSHT_IV_V_X_I class instead of VALU_IV_V_X_I.

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This allows us to remove the uimm5 argument and changes the
scheduler class from ALU to Shift.

Ultimately we need a WShift scheduler class, but we need to scrub
all of the crypto instructions for scheduler classes so I'll leave
that for future work.

Reviewed By: 4vtomat, ego

Differential Revision: https://reviews.llvm.org/D152030
This commit is contained in:
Craig Topper 2023-06-05 09:24:50 -07:00
parent e7c9481b70
commit 7a2b12b05b
2 changed files with 3 additions and 3 deletions
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4
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
View File

@ -442,14 +442,14 @@ multiclass VIndexLoadStore<list<int> EEWList> {
}
}
multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
ReadVIALUV_WorstCase, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase,
ReadVIALUX_WorstCase, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # ".vi", optype>,
def I : VALUVI<funct6, opcodestr # ".vi", simm5>,
Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
ReadVMask]>;
}

2
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
View File

@ -139,7 +139,7 @@ let Predicates = [HasStdExtZvbb] in {
defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in
defm VWSLL_V : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>;
defm VWSLL_V : VSHT_IV_V_X_I<"vwsll", 0b110101>;
} // Predicates = [HasStdExtZvbb]
let Predicates = [HasStdExtZvbc] in {