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R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SI
Other f64 opcodes not supported on SI can be lowered in a similar way. v2: use complex VOP3 patterns llvm-svn: 233076
This commit is contained in:
Marek Olsak
parent
43650e45c3
commit
7d77728c97
@ -202,10 +202,10 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
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if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
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setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::f64, Legal);
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setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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setOperationAction(ISD::FRINT, MVT::f64, Legal);
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}
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setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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setOperationAction(ISD::FDIV, MVT::f32, Custom);
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setOperationAction(ISD::FDIV, MVT::f64, Custom);
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@ -727,6 +727,26 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::V_CNDMASK_B64_PSEUDO: {
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unsigned Dst = MI->getOperand(0).getReg();
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unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
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unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
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unsigned Src0 = MI->getOperand(1).getReg();
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unsigned Src1 = MI->getOperand(2).getReg();
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const MachineOperand &SrcCond = MI->getOperand(3);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
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.addReg(RI.getSubReg(Src0, AMDGPU::sub0))
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.addReg(RI.getSubReg(Src1, AMDGPU::sub0))
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.addOperand(SrcCond);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
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.addReg(RI.getSubReg(Src0, AMDGPU::sub1))
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.addReg(RI.getSubReg(Src1, AMDGPU::sub1))
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.addOperand(SrcCond);
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MI->eraseFromParent();
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break;
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}
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}
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return true;
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}
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@ -320,6 +320,7 @@ def SIOperand {
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def SRCMODS {
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int NONE = 0;
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int NEG = 1;
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}
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def DSTCLAMP {
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@ -28,6 +28,8 @@ def SendMsgImm : Operand<i32> {
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def isGCN : Predicate<"Subtarget->getGeneration() "
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">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
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def isSI : Predicate<"Subtarget->getGeneration() "
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"== AMDGPUSubtarget::SOUTHERN_ISLANDS">;
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def isSICI : Predicate<
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"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
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"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
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@ -1874,6 +1876,11 @@ defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
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//===----------------------------------------------------------------------===//
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let isCodeGenOnly = 1, isPseudo = 1 in {
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// For use in patterns
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def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$dst),
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(ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []
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>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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// 64-bit vector move instruction. This is mainly used by the SIFoldOperands
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// pass to enable folding of inline immediates.
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@ -3320,6 +3327,50 @@ def : Pat <
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// Fract Patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI] in {
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// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
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// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient
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// way to implement it is using V_FRACT_F64.
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// The workaround for the V_FRACT bug is:
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// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999)
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// Convert (x + (-floor(x)) to fract(x)
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def : Pat <
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(f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
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(f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
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(V_CNDMASK_B64_PSEUDO
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$x,
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(V_MIN_F64
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SRCMODS.NONE,
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(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
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SRCMODS.NONE,
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(V_MOV_B64_PSEUDO 0x3fefffffffffffff),
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DSTCLAMP.NONE, DSTOMOD.NONE),
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(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/))
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>;
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// Convert floor(x) to (x - fract(x))
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def : Pat <
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(f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))),
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(V_ADD_F64
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$mods,
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$x,
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SRCMODS.NEG,
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(V_CNDMASK_B64_PSEUDO
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$x,
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(V_MIN_F64
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SRCMODS.NONE,
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(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
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SRCMODS.NONE,
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(V_MOV_B64_PSEUDO 0x3fefffffffffffff),
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DSTCLAMP.NONE, DSTOMOD.NONE),
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(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)),
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DSTCLAMP.NONE, DSTOMOD.NONE)
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>;
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} // End Predicates = [isSI]
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let Predicates = [isCI] in {
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// Convert (x - floor(x)) to fract(x)
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@ -1,7 +1,8 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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declare double @llvm.fabs.f64(double %Val)
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declare double @llvm.floor.f64(double) nounwind readnone
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declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
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declare <3 x double> @llvm.floor.v3f64(<3 x double>) nounwind readnone
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@ -11,24 +12,11 @@ declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
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; FUNC-LABEL: {{^}}ffloor_f64:
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; CI: v_floor_f64_e32
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; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
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; SI: s_lshr_b64
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; SI: s_not_b64
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; SI: s_and_b64
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; SI: cmp_gt_i32
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; SI: cndmask_b32
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; SI: cndmask_b32
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; SI: cmp_lt_i32
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; SI: cndmask_b32
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; SI: cndmask_b32
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; SI-DAG: v_cmp_gt_f64
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; SI-DAG: v_cmp_lg_f64
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; SI-DAG: s_and_b64
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; SI-DAG: v_cndmask_b32
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; SI-DAG: v_cndmask_b32
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; SI: v_fract_f64_e32
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; SI: v_min_f64
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; SI: v_cmp_class_f64_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_add_f64
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; SI: s_endpgm
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define void @ffloor_f64(double addrspace(1)* %out, double %x) {
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@ -37,6 +25,39 @@ define void @ffloor_f64(double addrspace(1)* %out, double %x) {
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ret void
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}
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; FUNC-LABEL: {{^}}ffloor_f64_neg:
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; CI: v_floor_f64_e64
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; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT:s[[0-9]+:[0-9]+]]]
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; SI: v_min_f64
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; SI: v_cmp_class_f64_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT]]
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; SI: s_endpgm
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define void @ffloor_f64_neg(double addrspace(1)* %out, double %x) {
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%neg = fsub double 0.0, %x
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%y = call double @llvm.floor.f64(double %neg) nounwind readnone
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store double %y, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ffloor_f64_neg_abs:
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; CI: v_floor_f64_e64
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; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT:s[[0-9]+:[0-9]+]]]|
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; SI: v_min_f64
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; SI: v_cmp_class_f64_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT]]|
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; SI: s_endpgm
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define void @ffloor_f64_neg_abs(double addrspace(1)* %out, double %x) {
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%abs = call double @llvm.fabs.f64(double %x)
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%neg = fsub double 0.0, %abs
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%y = call double @llvm.floor.f64(double %neg) nounwind readnone
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store double %y, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ffloor_v2f64:
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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60
llvm/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll
Normal file
60
llvm/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll
Normal file
@ -0,0 +1,60 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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declare double @llvm.fabs.f64(double %Val)
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declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone
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; FUNC-LABEL: {{^}}fract_f64:
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; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
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%val = load double, double addrspace(1)* %src, align 4
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%fract = call double @llvm.AMDGPU.fract.f64(double %val) nounwind readnone
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store double %fract, double addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fract_f64_neg:
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; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
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%val = load double, double addrspace(1)* %src, align 4
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%neg = fsub double 0.0, %val
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%fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
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store double %fract, double addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fract_f64_neg_abs:
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; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
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%val = load double, double addrspace(1)* %src, align 4
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%abs = call double @llvm.fabs.f64(double %val)
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%neg = fsub double 0.0, %abs
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%fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
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store double %fract, double addrspace(1)* %out, align 4
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ret void
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}
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