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Add some testcases for bitfields with illegal widths.
clang will generate IR like this for input using packed bitfields; very simple semantically, but it's a bit tricky to actually generate good code. llvm-svn: 296080
This commit is contained in:
Eli Friedman
parent
701ad3fbf9
commit
7e0ce82c4a
234
llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
Normal file
234
llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
Normal file
@ -0,0 +1,234 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE
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; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE
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define void @i24_or(i24* %a) {
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; LE-LABEL: i24_or:
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; LE: @ BB#0:
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; LE-NEXT: ldrh r1, [r0]
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; LE-NEXT: ldrb r2, [r0, #2]
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: strb r2, [r0, #2]
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; LE-NEXT: strh r1, [r0]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i24_or:
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; BE: @ BB#0:
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; BE-NEXT: ldrh r1, [r0]
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; BE-NEXT: ldrb r2, [r0, #2]
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; BE-NEXT: orr r1, r2, r1, lsl #8
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; BE-NEXT: orr r1, r1, #384
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; BE-NEXT: strb r1, [r0, #2]
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; BE-NEXT: lsr r1, r1, #8
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; BE-NEXT: strh r1, [r0]
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; BE-NEXT: mov pc, lr
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%aa = load i24, i24* %a, align 1
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%b = or i24 %aa, 384
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store i24 %b, i24* %a, align 1
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ret void
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}
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define void @i24_and_or(i24* %a) {
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; LE-LABEL: i24_and_or:
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; LE: @ BB#0:
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; LE-NEXT: ldrb r1, [r0, #2]
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; LE-NEXT: ldrh r2, [r0]
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; LE-NEXT: orr r1, r2, r1, lsl #16
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; LE-NEXT: ldr r2, .LCPI1_0
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: and r1, r1, r2
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; LE-NEXT: strh r1, [r0]
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; LE-NEXT: lsr r1, r1, #16
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; LE-NEXT: strb r1, [r0, #2]
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; LE-NEXT: mov pc, lr
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; LE-NEXT: .p2align 2
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; LE-NEXT: @ BB#1:
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; LE-NEXT: .LCPI1_0:
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; LE-NEXT: .long 16777088 @ 0xffff80
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;
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; BE-LABEL: i24_and_or:
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; BE: @ BB#0:
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; BE-NEXT: ldrh r1, [r0]
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; BE-NEXT: mov r2, #384
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; BE-NEXT: orr r1, r2, r1, lsl #8
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; BE-NEXT: ldr r2, .LCPI1_0
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; BE-NEXT: and r1, r1, r2
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; BE-NEXT: strb r1, [r0, #2]
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; BE-NEXT: lsr r1, r1, #8
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; BE-NEXT: strh r1, [r0]
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; BE-NEXT: mov pc, lr
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; BE-NEXT: .p2align 2
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; BE-NEXT: @ BB#1:
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; BE-NEXT: .LCPI1_0:
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; BE-NEXT: .long 16777088 @ 0xffff80
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%b = load i24, i24* %a, align 1
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%c = and i24 %b, -128
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%d = or i24 %c, 384
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
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; LE-LABEL: i24_insert_bit:
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; LE: @ BB#0:
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; LE-NEXT: ldrb r2, [r0, #2]
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; LE-NEXT: ldrh r3, [r0]
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; LE-NEXT: orr r2, r3, r2, lsl #16
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; LE-NEXT: ldr r3, .LCPI2_0
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; LE-NEXT: and r2, r2, r3
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; LE-NEXT: lsr r3, r2, #16
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; LE-NEXT: orr r1, r2, r1, lsl #13
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; LE-NEXT: strb r3, [r0, #2]
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; LE-NEXT: strh r1, [r0]
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; LE-NEXT: mov pc, lr
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; LE-NEXT: .p2align 2
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; LE-NEXT: @ BB#1:
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; LE-NEXT: .LCPI2_0:
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; LE-NEXT: .long 16769023 @ 0xffdfff
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;
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; BE-LABEL: i24_insert_bit:
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; BE: @ BB#0:
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; BE-NEXT: ldrh r2, [r0]
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; BE-NEXT: ldrb r3, [r0, #2]
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; BE-NEXT: orr r2, r3, r2, lsl #8
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; BE-NEXT: ldr r3, .LCPI2_0
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; BE-NEXT: and r2, r2, r3
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; BE-NEXT: orr r1, r2, r1, lsl #13
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; BE-NEXT: strb r2, [r0, #2]
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; BE-NEXT: lsr r1, r1, #8
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; BE-NEXT: strh r1, [r0]
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; BE-NEXT: mov pc, lr
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; BE-NEXT: .p2align 2
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; BE-NEXT: @ BB#1:
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; BE-NEXT: .LCPI2_0:
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; BE-NEXT: .long 16769023 @ 0xffdfff
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%extbit = zext i1 %bit to i24
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%b = load i24, i24* %a, align 1
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%extbit.shl = shl nuw nsw i24 %extbit, 13
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%c = and i24 %b, -8193
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%d = or i24 %c, %extbit.shl
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i56_or(i56* %a) {
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; LE-LABEL: i56_or:
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; LE: @ BB#0:
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; LE-NEXT: mov r2, r0
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; LE-NEXT: ldr r12, [r0]
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; LE-NEXT: ldrh r3, [r2, #4]!
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; LE-NEXT: ldrb r1, [r2, #2]
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; LE-NEXT: strb r1, [r2, #2]
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; LE-NEXT: orr r1, r12, #384
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; LE-NEXT: str r1, [r0]
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; LE-NEXT: strh r3, [r2]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i56_or:
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; BE: @ BB#0:
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; BE-NEXT: mov r1, r0
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; BE-NEXT: ldr r12, [r0]
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; BE-NEXT: ldrh r2, [r1, #4]!
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; BE-NEXT: ldrb r3, [r1, #2]
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; BE-NEXT: orr r2, r3, r2, lsl #8
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; BE-NEXT: orr r2, r2, r12, lsl #24
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; BE-NEXT: orr r2, r2, #384
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; BE-NEXT: lsr r3, r2, #8
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; BE-NEXT: strb r2, [r1, #2]
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; BE-NEXT: strh r3, [r1]
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; BE-NEXT: bic r1, r12, #255
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; BE-NEXT: orr r1, r1, r2, lsr #24
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; BE-NEXT: str r1, [r0]
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; BE-NEXT: mov pc, lr
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%aa = load i56, i56* %a
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%b = or i56 %aa, 384
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store i56 %b, i56* %a
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ret void
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}
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define void @i56_and_or(i56* %a) {
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; LE-LABEL: i56_and_or:
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; LE: @ BB#0:
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; LE-NEXT: mov r2, r0
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; LE-NEXT: ldr r1, [r0]
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; LE-NEXT: ldrh r12, [r2, #4]!
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; LE-NEXT: orr r1, r1, #384
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; LE-NEXT: ldrb r3, [r2, #2]
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; LE-NEXT: bic r1, r1, #127
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; LE-NEXT: strb r3, [r2, #2]
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; LE-NEXT: str r1, [r0]
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; LE-NEXT: strh r12, [r2]
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i56_and_or:
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; BE: @ BB#0:
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; BE-NEXT: .save {r11, lr}
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; BE-NEXT: push {r11, lr}
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; BE-NEXT: mov r2, r0
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; BE-NEXT: ldr lr, [r0]
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; BE-NEXT: mov r3, #128
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; BE-NEXT: ldrh r12, [r2, #4]!
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; BE-NEXT: strb r3, [r2, #2]
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; BE-NEXT: lsl r3, r12, #8
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; BE-NEXT: orr r3, r3, lr, lsl #24
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; BE-NEXT: orr r3, r3, #384
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; BE-NEXT: lsr r1, r3, #8
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; BE-NEXT: strh r1, [r2]
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; BE-NEXT: bic r1, lr, #255
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; BE-NEXT: orr r1, r1, r3, lsr #24
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; BE-NEXT: str r1, [r0]
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; BE-NEXT: pop {r11, lr}
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; BE-NEXT: mov pc, lr
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%b = load i56, i56* %a, align 1
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%c = and i56 %b, -128
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%d = or i56 %c, 384
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store i56 %d, i56* %a, align 1
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ret void
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}
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define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
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; LE-LABEL: i56_insert_bit:
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; LE: @ BB#0:
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; LE-NEXT: .save {r11, lr}
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; LE-NEXT: push {r11, lr}
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; LE-NEXT: mov r3, r0
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; LE-NEXT: ldr lr, [r0]
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; LE-NEXT: ldrh r12, [r3, #4]!
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; LE-NEXT: ldrb r2, [r3, #2]
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; LE-NEXT: strb r2, [r3, #2]
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; LE-NEXT: bic r2, lr, #8192
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; LE-NEXT: orr r1, r2, r1, lsl #13
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; LE-NEXT: str r1, [r0]
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; LE-NEXT: strh r12, [r3]
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; LE-NEXT: pop {r11, lr}
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; LE-NEXT: mov pc, lr
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;
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; BE-LABEL: i56_insert_bit:
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; BE: @ BB#0:
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; BE-NEXT: .save {r11, lr}
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; BE-NEXT: push {r11, lr}
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; BE-NEXT: mov r2, r0
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; BE-NEXT: ldr lr, [r0]
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; BE-NEXT: ldrh r12, [r2, #4]!
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; BE-NEXT: ldrb r3, [r2, #2]
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; BE-NEXT: orr r12, r3, r12, lsl #8
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; BE-NEXT: orr r3, r12, lr, lsl #24
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; BE-NEXT: bic r3, r3, #8192
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; BE-NEXT: orr r1, r3, r1, lsl #13
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; BE-NEXT: strb r3, [r2, #2]
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; BE-NEXT: lsr r3, r1, #8
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; BE-NEXT: strh r3, [r2]
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; BE-NEXT: bic r2, lr, #255
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; BE-NEXT: orr r1, r2, r1, lsr #24
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; BE-NEXT: str r1, [r0]
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; BE-NEXT: pop {r11, lr}
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; BE-NEXT: mov pc, lr
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%extbit = zext i1 %bit to i56
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%b = load i56, i56* %a, align 1
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%extbit.shl = shl nuw nsw i56 %extbit, 13
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%c = and i56 %b, -8193
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%d = or i56 %c, %extbit.shl
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store i56 %d, i56* %a, align 1
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ret void
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}
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144
llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
Normal file
144
llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
Normal file
@ -0,0 +1,144 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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define void @i24_or(i24* %a) {
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; CHECK-LABEL: i24_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: movzbl 2(%rdi), %ecx
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; CHECK-NEXT: movb %cl, 2(%rdi)
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: orl $384, %ecx # imm = 0x180
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; CHECK-NEXT: movw %cx, (%rdi)
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; CHECK-NEXT: retq
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%aa = load i24, i24* %a, align 1
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%b = or i24 %aa, 384
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store i24 %b, i24* %a, align 1
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ret void
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}
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define void @i24_and_or(i24* %a) {
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; CHECK-LABEL: i24_and_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: movzbl 2(%rdi), %ecx
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: orl $384, %ecx # imm = 0x180
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; CHECK-NEXT: andl $16777088, %ecx # imm = 0xFFFF80
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; CHECK-NEXT: movw %cx, (%rdi)
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; CHECK-NEXT: shrl $16, %ecx
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; CHECK-NEXT: movb %cl, 2(%rdi)
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; CHECK-NEXT: retq
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%b = load i24, i24* %a, align 1
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%c = and i24 %b, -128
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%d = or i24 %c, 384
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
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; CHECK-LABEL: i24_insert_bit:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: movzwl (%rdi), %ecx
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; CHECK-NEXT: movzbl 2(%rdi), %edx
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; CHECK-NEXT: shll $16, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: shll $13, %eax
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; CHECK-NEXT: andl $16769023, %edx # imm = 0xFFDFFF
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: shrl $16, %edx
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; CHECK-NEXT: movb %dl, 2(%rdi)
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; CHECK-NEXT: movw %ax, (%rdi)
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; CHECK-NEXT: retq
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%extbit = zext i1 %bit to i24
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%b = load i24, i24* %a, align 1
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%extbit.shl = shl nuw nsw i24 %extbit, 13
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%c = and i24 %b, -8193
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%d = or i24 %c, %extbit.shl
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i56_or(i56* %a) {
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; CHECK-LABEL: i56_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl 4(%rdi), %eax
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; CHECK-NEXT: movzbl 6(%rdi), %ecx
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; CHECK-NEXT: movl (%rdi), %edx
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; CHECK-NEXT: movb %cl, 6(%rdi)
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; CHECK-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: shlq $32, %rcx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: orq $384, %rdx # imm = 0x180
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; CHECK-NEXT: movl %edx, (%rdi)
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; CHECK-NEXT: shrq $32, %rdx
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; CHECK-NEXT: movw %dx, 4(%rdi)
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; CHECK-NEXT: retq
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%aa = load i56, i56* %a, align 1
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%b = or i56 %aa, 384
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store i56 %b, i56* %a, align 1
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ret void
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}
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define void @i56_and_or(i56* %a) {
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; CHECK-LABEL: i56_and_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl 4(%rdi), %eax
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; CHECK-NEXT: movzbl 6(%rdi), %ecx
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: shlq $32, %rcx
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: orq %rcx, %rax
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; CHECK-NEXT: orq $384, %rax # imm = 0x180
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; CHECK-NEXT: movabsq $72057594037927808, %rcx # imm = 0xFFFFFFFFFFFF80
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; CHECK-NEXT: andq %rax, %rcx
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; CHECK-NEXT: movl %ecx, (%rdi)
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; CHECK-NEXT: movq %rcx, %rax
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; CHECK-NEXT: shrq $48, %rax
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; CHECK-NEXT: movb %al, 6(%rdi)
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; CHECK-NEXT: shrq $32, %rcx
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; CHECK-NEXT: movw %cx, 4(%rdi)
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; CHECK-NEXT: retq
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%b = load i56, i56* %a, align 1
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%c = and i56 %b, -128
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%d = or i56 %c, 384
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store i56 %d, i56* %a, align 1
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ret void
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}
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define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
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; CHECK-LABEL: i56_insert_bit:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: movzwl 4(%rdi), %ecx
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; CHECK-NEXT: movzbl 6(%rdi), %edx
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; CHECK-NEXT: shll $16, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: shlq $32, %rdx
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; CHECK-NEXT: movl (%rdi), %ecx
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; CHECK-NEXT: orq %rdx, %rcx
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; CHECK-NEXT: shlq $13, %rax
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; CHECK-NEXT: movabsq $72057594037919743, %rdx # imm = 0xFFFFFFFFFFDFFF
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; CHECK-NEXT: andq %rcx, %rdx
|
||||
; CHECK-NEXT: orq %rdx, %rax
|
||||
; CHECK-NEXT: shrq $48, %rdx
|
||||
; CHECK-NEXT: movb %dl, 6(%rdi)
|
||||
; CHECK-NEXT: movl %eax, (%rdi)
|
||||
; CHECK-NEXT: shrq $32, %rax
|
||||
; CHECK-NEXT: movw %ax, 4(%rdi)
|
||||
; CHECK-NEXT: retq
|
||||
%extbit = zext i1 %bit to i56
|
||||
%b = load i56, i56* %a, align 1
|
||||
%extbit.shl = shl nuw nsw i56 %extbit, 13
|
||||
%c = and i56 %b, -8193
|
||||
%d = or i56 %c, %extbit.shl
|
||||
store i56 %d, i56* %a, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -121,6 +121,7 @@ def build_function_body_dictionary(raw_tool_output, triple, prefixes, func_dict,
|
||||
'x86': (scrub_asm_x86, ASM_FUNCTION_X86_RE),
|
||||
'i386': (scrub_asm_x86, ASM_FUNCTION_X86_RE),
|
||||
'arm-eabi': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
|
||||
'armeb-eabi': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
|
||||
'powerpc64le': (scrub_asm_powerpc64le, ASM_FUNCTION_PPC_RE),
|
||||
}
|
||||
handlers = None
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user