Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-12-23 16:06:24 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

[Target] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

Browse Source 
llvm-svn: 305757
This commit is contained in:
Eugene Zelenko 2017-06-19 22:43:19 +00:00
parent 7ba830d61c
commit 8361b0a9bb
8 changed files with 170 additions and 127 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -1,4 +1,4 @@
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
//===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -14,36 +14,46 @@
#ifndef LLVM_TARGET_TARGETINSTRINFO_H
#define LLVM_TARGET_TARGETINSTRINFO_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/DenseMapInfo.h"
#include "llvm/ADT/None.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <utility>
#include <vector>
namespace llvm {
class DFAPacketizer;
class InstrItineraryData;
class LiveVariables;
class MCAsmInfo;
class MachineMemOperand;
class MachineRegisterInfo;
class MDNode;
class MCAsmInfo;
class MCInst;
struct MCSchedModel;
class MCSymbolRefExpr;
class SDNode;
class ScheduleHazardRecognizer;
class SelectionDAG;
class Module;
class ScheduleDAG;
class ScheduleHazardRecognizer;
class SDNode;
class SelectionDAG;
class RegScavenger;
class TargetRegisterClass;
class TargetRegisterInfo;
class TargetSubtargetInfo;
class TargetSchedModel;
class DFAPacketizer;
class TargetSubtargetInfo;
template<class T> class SmallVectorImpl;
@ -52,8 +62,6 @@ template<class T> class SmallVectorImpl;
/// TargetInstrInfo - Interface to description of machine instruction set
///
class TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo(const TargetInstrInfo &) = delete;
void operator=(const TargetInstrInfo &) = delete;
public:
TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
@ -61,7 +69,8 @@ public:
CallFrameDestroyOpcode(CFDestroyOpcode),
CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}
TargetInstrInfo(const TargetInstrInfo &) = delete;
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();
static bool isGenericOpcode(unsigned Opc) {
@ -396,14 +405,17 @@ public:
struct RegSubRegPair {
unsigned Reg;
unsigned SubReg;
RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
: Reg(Reg), SubReg(SubReg) {}
};
/// A pair composed of a pair of a register and a sub-register index,
/// and another sub-register index.
/// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
struct RegSubRegPairAndIdx : RegSubRegPair {
unsigned SubIdx;
RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
unsigned SubIdx = 0)
: RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
@ -469,7 +481,6 @@ public:
RegSubRegPair &BaseReg,
RegSubRegPairAndIdx &InsertedReg) const;
/// Return true if two machine instructions would produce identical values.
/// By default, this is only true when the two instructions
/// are deemed identical except for defs. If this function is called when the
@ -551,23 +562,19 @@ public:
PRED_INVALID // Sentinel value
};
ComparePredicate Predicate;
MachineOperand LHS;
MachineOperand RHS;
MachineBasicBlock *TrueDest;
MachineBasicBlock *FalseDest;
MachineInstr *ConditionDef;
ComparePredicate Predicate = PRED_INVALID;
MachineOperand LHS = MachineOperand::CreateImm(0);
MachineOperand RHS = MachineOperand::CreateImm(0);
MachineBasicBlock *TrueDest = nullptr;
MachineBasicBlock *FalseDest = nullptr;
MachineInstr *ConditionDef = nullptr;
/// SingleUseCondition is true if ConditionDef is dead except for the
/// branch(es) at the end of the basic block.
///
bool SingleUseCondition;
bool SingleUseCondition = false;
explicit MachineBranchPredicate()
: Predicate(PRED_INVALID), LHS(MachineOperand::CreateImm(0)),
RHS(MachineOperand::CreateImm(0)), TrueDest(nullptr),
FalseDest(nullptr), ConditionDef(nullptr), SingleUseCondition(false) {
}
explicit MachineBranchPredicate() = default;
};
/// Analyze the branching code at the end of MBB and parse it into the
@ -1117,7 +1124,6 @@ public:
virtual void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
/// Return the noop instruction to use for a noop.
virtual void getNoop(MCInst &NopInst) const;
@ -1621,16 +1627,18 @@ private:
/// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
template<>
struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
typedef DenseMapInfo<unsigned> RegInfo;
using RegInfo = DenseMapInfo<unsigned>;
static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
RegInfo::getEmptyKey());
}
static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
RegInfo::getTombstoneKey());
}
/// \brief Reuse getHashValue implementation from
/// std::pair<unsigned, unsigned>.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
@ -1638,6 +1646,7 @@ struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
std::make_pair(Val.Reg, Val.SubReg);
return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
}
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
const TargetInstrInfo::RegSubRegPair &RHS) {
return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&

60
llvm/include/llvm/Target/TargetLowering.h
View File

@ -1,4 +1,4 @@
//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
//===- llvm/Target/TargetLowering.h - Target Lowering Info ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -23,6 +23,7 @@
#ifndef LLVM_TARGET_TARGETLOWERING_H
#define LLVM_TARGET_TARGETLOWERING_H
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
@ -40,6 +41,7 @@
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
@ -66,10 +68,13 @@ namespace llvm {
class BranchProbability;
class CCState;
class CCValAssign;
class Constant;
class FastISel;
class FunctionLoweringInfo;
class GlobalValue;
class IntrinsicInst;
struct KnownBits;
class LLVMContext;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
@ -78,6 +83,7 @@ class MachineLoop;
class MachineRegisterInfo;
class MCContext;
class MCExpr;
class Module;
class TargetRegisterClass;
class TargetLibraryInfo;
class TargetRegisterInfo;
@ -127,7 +133,7 @@ public:
/// LegalizeKind holds the legalization kind that needs to happen to EVT
/// in order to type-legalize it.
typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
/// Enum that describes how the target represents true/false values.
enum BooleanContent {
@ -189,7 +195,7 @@ public:
void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
};
typedef std::vector<ArgListEntry> ArgListTy;
using ArgListTy = std::vector<ArgListEntry>;
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
ArgListTy &Args) const {};
@ -211,8 +217,8 @@ public:
/// NOTE: The TargetMachine owns TLOF.
explicit TargetLoweringBase(const TargetMachine &TM);
TargetLoweringBase(const TargetLoweringBase&) = delete;
void operator=(const TargetLoweringBase&) = delete;
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase() = default;
protected:
@ -2455,8 +2461,8 @@ class TargetLowering : public TargetLoweringBase {
public:
struct DAGCombinerInfo;
TargetLowering(const TargetLowering&) = delete;
void operator=(const TargetLowering&) = delete;
TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;
/// NOTE: The TargetMachine owns TLOF.
explicit TargetLowering(const TargetMachine &TM);
@ -2772,7 +2778,6 @@ public:
/// described by the Ins array, into the specified DAG. The implementation
/// should fill in the InVals array with legal-type argument values, and
/// return the resulting token chain value.
///
virtual SDValue LowerFormalArguments(
SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
@ -2786,7 +2791,7 @@ public:
/// implementation.
struct CallLoweringInfo {
SDValue Chain;
Type *RetTy;
Type *RetTy = nullptr;
bool RetSExt : 1;
bool RetZExt : 1;
bool IsVarArg : 1;
@ -2794,30 +2799,28 @@ public:
bool DoesNotReturn : 1;
bool IsReturnValueUsed : 1;
bool IsConvergent : 1;
bool IsPatchPoint : 1;
// IsTailCall should be modified by implementations of
// TargetLowering::LowerCall that perform tail call conversions.
bool IsTailCall;
bool IsTailCall = false;
unsigned NumFixedArgs;
CallingConv::ID CallConv;
unsigned NumFixedArgs = -1;
CallingConv::ID CallConv = CallingConv::C;
SDValue Callee;
ArgListTy Args;
SelectionDAG &DAG;
SDLoc DL;
ImmutableCallSite *CS;
bool IsPatchPoint;
ImmutableCallSite *CS = nullptr;
SmallVector<ISD::OutputArg, 32> Outs;
SmallVector<SDValue, 32> OutVals;
SmallVector<ISD::InputArg, 32> Ins;
SmallVector<SDValue, 4> InVals;
CallLoweringInfo(SelectionDAG &DAG)
: RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
IsConvergent(false), IsTailCall(false), NumFixedArgs(-1),
CallConv(CallingConv::C), DAG(DAG), CS(nullptr), IsPatchPoint(false) {
}
: RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
IsPatchPoint(false), DAG(DAG) {}
CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
DL = dl;
@ -3091,7 +3094,6 @@ public:
return nullptr;
}
bool verifyReturnAddressArgumentIsConstant(SDValue Op,
SelectionDAG &DAG) const;
@ -3140,15 +3142,19 @@ public:
/// Information about the constraint code, e.g. Register, RegisterClass,
/// Memory, Other, Unknown.
TargetLowering::ConstraintType ConstraintType;
TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
/// If this is the result output operand or a clobber, this is null,
/// otherwise it is the incoming operand to the CallInst. This gets
/// modified as the asm is processed.
Value *CallOperandVal;
Value *CallOperandVal = nullptr;
/// The ValueType for the operand value.
MVT ConstraintVT;
MVT ConstraintVT = MVT::Other;
/// Copy constructor for copying from a ConstraintInfo.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
: InlineAsm::ConstraintInfo(std::move(Info)) {}
/// Return true of this is an input operand that is a matching constraint
/// like "4".
@ -3157,15 +3163,9 @@ public:
/// If this is an input matching constraint, this method returns the output
/// operand it matches.
unsigned getMatchedOperand() const;
/// Copy constructor for copying from a ConstraintInfo.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
: InlineAsm::ConstraintInfo(std::move(Info)),
ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
ConstraintVT(MVT::Other) {}
};
typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
/// Split up the constraint string from the inline assembly value into the
/// specific constraints and their prefixes, and also tie in the associated

58
llvm/include/llvm/Target/TargetRegisterInfo.h
View File

@ -1,4 +1,4 @@
//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
//==- Target/TargetRegisterInfo.h - Target Register Information --*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -17,30 +17,35 @@
#define LLVM_TARGET_TARGETREGISTERINFO_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Printable.h"
#include <cassert>
#include <cstdint>
#include <functional>
namespace llvm {
class BitVector;
class MachineFunction;
class RegScavenger;
template<class T> class SmallVectorImpl;
class VirtRegMap;
class raw_ostream;
class LiveRegMatrix;
class MachineFunction;
class MachineInstr;
class RegScavenger;
class VirtRegMap;
class TargetRegisterClass {
public:
typedef const MCPhysReg* iterator;
typedef const MCPhysReg* const_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
using iterator = const MCPhysReg *;
using const_iterator = const MCPhysReg *;
using sc_iterator = const TargetRegisterClass* const *;
// Instance variables filled by tablegen, do not use!
const MCRegisterClass *MC;
@ -151,7 +156,6 @@ public:
/// There exists SuperRC where:
/// For all Reg in SuperRC:
/// this->contains(Reg:Idx)
///
const uint16_t *getSuperRegIndices() const {
return SuperRegIndices;
}
@ -182,7 +186,6 @@ public:
/// other criteria.
///
/// By default, this method returns all registers in the class.
///
ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
}
@ -217,8 +220,9 @@ struct RegClassWeight {
///
class TargetRegisterInfo : public MCRegisterInfo {
public:
typedef const TargetRegisterClass * const * regclass_iterator;
typedef const MVT::SimpleValueType* vt_iterator;
using regclass_iterator = const TargetRegisterClass * const *;
using vt_iterator = const MVT::SimpleValueType *;
private:
const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
const char *const *SubRegIndexNames; // Names of subreg indexes.
@ -236,8 +240,8 @@ protected:
const LaneBitmask *SRILaneMasks,
LaneBitmask CoveringLanes);
virtual ~TargetRegisterInfo();
public:
public:
// Register numbers can represent physical registers, virtual registers, and
// sometimes stack slots. The unsigned values are divided into these ranges:
//
@ -510,7 +514,7 @@ public:
/// Prior to adding the live-out mask to a stackmap or patchpoint
/// instruction, provide the target the opportunity to adjust it (mainly to
/// remove pseudo-registers that should be ignored).
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const { }
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
/// Return a super-register of the specified register
/// Reg so its sub-register of index SubIdx is Reg.
@ -568,7 +572,6 @@ public:
/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
/// ssub_0:S0 - ssub_3:S3 subregs.
/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
///
unsigned composeSubRegIndices(unsigned a, unsigned b) const {
if (!a) return b;
if (!b) return a;
@ -643,7 +646,6 @@ public:
/// corresponding argument register class.
///
/// The function returns NULL if no register class can be found.
///
const TargetRegisterClass*
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
const TargetRegisterClass *RCB, unsigned SubB,
@ -654,7 +656,6 @@ public:
//
/// Register class iterators
///
regclass_iterator regclass_begin() const { return RegClassBegin; }
regclass_iterator regclass_end() const { return RegClassEnd; }
iterator_range<regclass_iterator> regclasses() const {
@ -909,7 +910,6 @@ public:
/// Return true if the register was spilled, false otherwise.
/// If this function does not spill the register, the scavenger
/// will instead spill it to the emergency spill slot.
///
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator &UseMI,
@ -968,7 +968,6 @@ public:
ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
};
//===----------------------------------------------------------------------===//
// SuperRegClassIterator
//===----------------------------------------------------------------------===//
@ -987,7 +986,7 @@ public:
//
class SuperRegClassIterator {
const unsigned RCMaskWords;
unsigned SubReg;
unsigned SubReg = 0;
const uint16_t *Idx;
const uint32_t *Mask;
@ -998,9 +997,7 @@ public:
const TargetRegisterInfo *TRI,
bool IncludeSelf = false)
: RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
SubReg(0),
Idx(RC->getSuperRegIndices()),
Mask(RC->getSubClassMask()) {
Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
if (!IncludeSelf)
++*this;
}
@ -1039,12 +1036,12 @@ class BitMaskClassIterator {
/// Base index of CurrentChunk.
/// In other words, the number of bit we read to get at the
/// beginning of that chunck.
unsigned Base;
unsigned Base = 0;
/// Adjust base index of CurrentChunk.
/// Base index + how many bit we read within CurrentChunk.
unsigned Idx;
unsigned Idx = 0;
/// Current register class ID.
unsigned ID;
unsigned ID = 0;
/// Mask we are iterating over.
const uint32_t *Mask;
/// Current chunk of the Mask we are traversing.
@ -1098,8 +1095,7 @@ public:
///
/// \pre \p Mask != nullptr
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
: NumRegClasses(TRI.getNumRegClasses()), Base(0), Idx(0), ID(0),
Mask(Mask), CurrentChunk(*Mask) {
: NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
// Move to the first ID.
moveToNextID();
}
@ -1151,6 +1147,6 @@ Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
/// registers on a \ref raw_ostream.
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
} // End llvm namespace
} // end namespace llvm
#endif
#endif // LLVM_TARGET_TARGETREGISTERINFO_H

24
llvm/include/llvm/Target/TargetSubtargetInfo.h
View File

@ -1,4 +1,4 @@
//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
//===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -20,21 +20,29 @@
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h"
#include <memory>
#include <vector>
namespace llvm {
class CallLowering;
class InstrItineraryData;
struct InstrStage;
class InstructionSelector;
class LegalizerInfo;
class MachineInstr;
struct MachineSchedPolicy;
struct MCReadAdvanceEntry;
struct MCWriteLatencyEntry;
struct MCWriteProcResEntry;
class RegisterBankInfo;
class SDep;
class SelectionDAGTargetInfo;
struct SubtargetFeatureKV;
struct SubtargetInfoKV;
class SUnit;
class TargetFrameLowering;
class TargetInstrInfo;
@ -42,7 +50,7 @@ class TargetLowering;
class TargetRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
struct MachineSchedPolicy;
class Triple;
//===----------------------------------------------------------------------===//
///
@ -64,13 +72,13 @@ protected: // Can only create subclasses...
public:
// AntiDepBreakMode - Type of anti-dependence breaking that should
// be performed before post-RA scheduling.
typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
TargetSubtargetInfo() = delete;
TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
void operator=(const TargetSubtargetInfo &) = delete;
virtual ~TargetSubtargetInfo();
TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
~TargetSubtargetInfo() override;
virtual bool isXRaySupported() const { return false; }
@ -112,7 +120,6 @@ public:
/// getRegisterInfo - If register information is available, return it. If
/// not, return null.
///
virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
/// If the information for the register banks is available, return it.
@ -121,7 +128,6 @@ public:
/// getInstrItineraryData - Returns instruction itinerary data for the target
/// or specific subtarget.
///
virtual const InstrItineraryData *getInstrItineraryData() const {
return nullptr;
}

20
llvm/lib/CodeGen/TargetRegisterInfo.cpp
View File

@ -1,4 +1,4 @@
//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
//
// The LLVM Compiler Infrastructure
//
@ -11,17 +11,27 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <utility>
#define DEBUG_TYPE "target-reg-info"
@ -38,7 +48,7 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
CoveringLanes(SRICoveringLanes) {
}
TargetRegisterInfo::~TargetRegisterInfo() {}
TargetRegisterInfo::~TargetRegisterInfo() = default;
void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
const {
@ -126,7 +136,7 @@ Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
});
}
} // End of llvm namespace
} // end namespace llvm
/// getAllocatableClass - Return the maximal subclass of the given register
/// class that is alloctable, or NULL.

14
llvm/lib/CodeGen/TargetSubtargetInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
//
// The LLVM Compiler Infrastructure
//
@ -11,15 +11,17 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include <string>
using namespace llvm;
//---------------------------------------------------------------------------
// TargetSubtargetInfo Class
//
TargetSubtargetInfo::TargetSubtargetInfo(
const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
@ -29,7 +31,7 @@ TargetSubtargetInfo::TargetSubtargetInfo(
: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
}
TargetSubtargetInfo::~TargetSubtargetInfo() {}
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
bool TargetSubtargetInfo::enableAtomicExpand() const {
return true;

32
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
View File

@ -1,4 +1,4 @@
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,13 +11,23 @@
//
//===----------------------------------------------------------------------===//
#include "HexagonSubtarget.h"
#include "Hexagon.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
#include <cassert>
#include <map>
using namespace llvm;
@ -119,9 +129,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
StringRef FS, const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering() {
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {
initializeEnvironment();
// Initialize scheduling itinerary for the specified CPU.
@ -196,7 +204,6 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
updateLatency(*SrcInst, *DstInst, Dep);
}
void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
for (auto &SU : DAG->SUnits) {
if (!SU.isInstr())
@ -240,18 +247,18 @@ void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
}
}
void HexagonSubtarget::getPostRAMutations(
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
Mutations.push_back(
llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
}
void HexagonSubtarget::getSMSMutations(
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
Mutations.push_back(
llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
}
// Pin the vtable to this file.
void HexagonSubtarget::anchor() {}
@ -447,4 +454,3 @@ unsigned HexagonSubtarget::getL1PrefetchDistance() const {
bool HexagonSubtarget::enableSubRegLiveness() const {
return EnableSubregLiveness;
}

22
llvm/lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -1,4 +1,4 @@
//===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -15,12 +15,17 @@
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
#include "HexagonFrameLowering.h"
#include "HexagonISelLowering.h"
#include "HexagonInstrInfo.h"
#include "HexagonISelLowering.h"
#include "HexagonSelectionDAGInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <memory>
#include <string>
#include <vector>
#define GET_SUBTARGETINFO_HEADER
#include "HexagonGenSubtargetInfo.inc"
@ -30,6 +35,12 @@
namespace llvm {
class MachineInstr;
class SDep;
class SUnit;
class TargetMachine;
class Triple;
class HexagonSubtarget : public HexagonGenSubtargetInfo {
virtual void anchor();
@ -57,6 +68,7 @@ private:
HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering;
InstrItineraryData InstrItins;
void initializeEnvironment();
public:
@ -108,6 +120,7 @@ public:
bool useBSBScheduling() const { return UseBSBScheduling; }
bool enableMachineScheduler() const override;
// Always use the TargetLowering default scheduler.
// FIXME: This will use the vliw scheduler which is probably just hurting
// compiler time and will be removed eventually anyway.
@ -124,6 +137,7 @@ public:
unsigned getSmallDataThreshold() const {
return Hexagon_SMALL_DATA_THRESHOLD;
}
const HexagonArchEnum &getHexagonArchVersion() const {
return HexagonArchVersion;
}
@ -155,4 +169,4 @@ private:
} // end namespace llvm
#endif
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H